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| MB86296S PCI Graphics Controller Specification Revision 0.1 17th Mar,200 4 Copyright (c) FUJITSU LIMITED 2003-2004 ALL RIGHTS RESERVED * The specifications in this manual are subject to change without notice. Contact our Sales Department before purchasing the product described in this manual. * Information and circuit diagrams in this manual are only examples of device applications, they are not intended to be used in actual equipment. Also, Fujitsu accepts no responsibility for infringement of patents or other rights owned by third parties caused by use of the information and circuit diagrams. * * The contents of this manual must not be reprinted or duplicated without permission of Fujitsu. Fujitsu's semiconductor devices are intended for standard uses (such as office equipment (computers and OA equipment), industrial/communications/measuring equipment, and personal/home equipment). Customers using semiconductor devices for special applications (including aerospace, nuclear, military and medical applications) in which a failure or malfunction might endanger life or limb and which require extremely high reliability must contact our Sales Department first. If damage is caused by such use of our semiconductor devices without first consulting our Sales Department, Fujitsu will not assume any responsibility for the loss. Semiconductor devices fail with a known probability. Customers must use safety design (such as redundant design, fireproof design, over-current prevention design, and malfunction prevention design) so that failures will not cause accidents, injury or death). * If the products described in this manual fall within the goods or technologies regulated by the Foreign Exchange and Foreign Trade Law, permission must be obtained before exporting the goods or technologies. * CAUTION Burns There is a danger of burns because the IC surface is heated depending on the IC operating conditions. In this case, take safety measures. All Rights Reserved The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. ii Update history Date 17.3.2004 Version Page count 0.1 347 Change First edition (update from Coral-P specification) MB86296S iii 1. GENERAL CONTENTS 2. PINS 1.1 Preface ........................................................................................................................................... 1 1.2 Features ......................................................................................................................................... 2 1.3 Block Diagram ................................................................................................................................ 3 1.4 Functional Overview....................................................................................................................... 4 1.4.1 Host CPU interface .................................................................................................................. 4 1.4.2 External memory interface ....................................................................................................... 5 1.4.3 Display controller...................................................................................................................... 6 1.4.4 Video capture function.............................................................................................................. 8 1.4.5 Geometry processing ............................................................................................................... 9 1.4.6 2D Drawing............................................................................................................................. 10 1.4.7 3D Drawing............................................................................................................................. 12 1.4.8 Special effects ........................................................................................................................ 13 1.4.9 Others..................................................................................................................................... 15 2.1 Signals.......................................................................................................................................... 16 2.1.1 Signal lines ............................................................................................................................. 16 2.2 Pin Assignment............................................................................................................................. 17 2.2.1 Pin assignment diagram......................................................................................................... 17 2.2.2 Pin assignment table.............................................................................................................. 18 2.3 Pin Function.................................................................................................................................. 26 2.3.1 Host CPU interface ................................................................................................................ 26 2.3.2 Video output interface ............................................................................................................ 28 2.3.3 Video capture interface .......................................................................................................... 30 2.3.4 I2C interface............................................................................................................................ 31 2.3.5 Graphics memory interface.................................................................................................... 32 2.3.6 Clock input.............................................................................................................................. 33 2.3.7 Test pins ................................................................................................................................. 34 2.3.8 Reset sequence ..................................................................................................................... 34 2.3.9 How to switch internal operating frequency ........................................................................... 34 3.1. Hardware reset ............................................................................................................................. 35 3.2. Re-reset........................................................................................................................................ 35 3.3. Software reset ........................................................................................................................... 35 4.1 Standard PCI Slave Accesses .................................................................................................... 36 4.1.1 PCI Slave Write...................................................................................................................... 36 4.1.2 PCI Slave Read...................................................................................................................... 36 4.2 Burst Controller Accesses (including PCI Master)...................................................................... 36 4.2.1 Transfer Modes ..................................................................................................................... 37 4.2.2 Burst Controller Control/Status.............................................................................................. 38 4.3 FIFO Transfers............................................................................................................................ 39 4.4 GPIO/Serial Interface.................................................................................................................. 39 4.4.1 GPIO ....................................................................................................................................... 39 4.4.2 Serial Interface ........................................................................................................................ 39 4.5 Interrupt....................................................................................................................................... 40 4.5.1 Address Error Interrupt............................................................................................................ 40 4.6 Memory Map ............................................................................................................................... 41 1 16 3. PROCEDURE OF THE HARDWARE INITIALIZATION 4. HOST INTERFACE 35 36 5. I2C Interface Controller MB86296S iv 43 6. Graphics Memory 5.1 Features ........................................................................................................................................ 43 5.2 Block diagram................................................................................................................................ 44 5.2.1 Block Diagram......................................................................................................................... 44 5.2.2 Block Function Overview......................................................................................................... 45 5.3 Example application ...................................................................................................................... 46 5.3.1 Connection Diagram ............................................................................................................... 46 5.4 Function overview.......................................................................................................................... 47 5.4.1 START condition...................................................................................................................... 47 5.4.2 STOP condition ....................................................................................................................... 47 5.4.3 Addressing............................................................................................................................... 48 5.4.4 Synchronization of SCL........................................................................................................... 48 5.4.5 Arbitration ................................................................................................................................ 49 5.4.6 Acknowledge ........................................................................................................................... 49 5.4.7 Bus error.................................................................................................................................. 49 5.4.8 Initialize ................................................................................................................................... 50 5.4.9 1-byte transfer from master to slave ....................................................................................... 51 5.4.10 1 byte transfer from slave to master ..................................................................................... 52 5.4.11 Recovery from bus error........................................................................................................ 53 5.5 Note ............................................................................................................................................... 54 6.1. Configuration ................................................................................................................................ 55 6.1.1. Data type ................................................................................................................................ 55 6.1.2. Memory Mapping.................................................................................................................... 56 6.1.3. Data Format ........................................................................................................................... 56 6.2. Frame Management ..................................................................................................................... 58 6.2.1. Single Buffer........................................................................................................................... 58 6.2.2. Double Buffer ......................................................................................................................... 58 6.3. Memory Access ............................................................................................................................ 58 6.3.1. Memory Access by host CPU................................................................................................. 58 6.3.2. Priority of memory accessing................................................................................................. 58 6.4. Connection with memory.............................................................................................................. 59 6.4.1. Connection with memory........................................................................................................ 59 7.1 Overview....................................................................................................................................... 60 7.2 Display Function ........................................................................................................................... 61 7.2.1 Layer configuration................................................................................................................. 61 7.2.2 Overlay................................................................................................................................... 62 7.2.3 Display parameters ................................................................................................................ 64 7.2.4 Display position control .......................................................................................................... 65 7.3 Display Color ................................................................................................................................ 67 7.4 Cursor........................................................................................................................................... 68 7.4.1 Cursor display function........................................................................................................... 68 7.4.2 Cursor control......................................................................................................................... 68 7.5 Display Scan Control.................................................................................................................... 69 7.5.1 Applicable display................................................................................................................... 69 7.5.2 Interlace display ..................................................................................................................... 70 7.6 Video Interface, NTSC/PAL Output .............................................................................................. 71 7.7 Programmable YCbCr/RGB conversion for L1-layer display ........................................................ 72 7.8 DCLKO shift ................................................................................................................................ 74 7.9 Syncronous register update of display........................................................................................ 74 55 7. DISPLAY CONTROLLER 60 MB86296S v 8. Video Capture 7.10 Dual Display ................................................................................................................................ 75 9. GEOMETRY ENGINE 8.1 Video Capture function .................................................................................................................. 77 8.1.1 Input data Formats .................................................................................................................. 77 8.1.2 Capturing of Video Signal ....................................................................................................... 77 8.1.3 Non-interlace Transformation.................................................................................................. 77 8.2 Video Buffer................................................................................................................................... 78 8.2.1 Data Form ............................................................................................................................... 78 8.2.2 Synchronous Control............................................................................................................... 78 8.2.3 Area Allocation......................................................................................................................... 78 8.2.4 Window Display....................................................................................................................... 79 8.2.5 Interlace Display...................................................................................................................... 79 8.3 Scaling........................................................................................................................................... 80 8.3.1 Down-scaling Function............................................................................................................ 80 8.3.2 Up-scaling Function ................................................................................................................ 80 8.3.2 Flow of image processing ....................................................................................................... 82 8.4 Error handling ................................................................................................................................ 85 8.4.1 Error detect function................................................................................................................ 85 8.5 External video signal input conditions ........................................................................................... 86 8.5.1 RTB656 YUV422 input format................................................................................................. 86 8.5.2 RGB input format..................................................................................................................... 88 77 10. DRAWING PROCESSING 9.1 Geometry Pipeline........................................................................................................................ 94 9.1.1 Processing flow ...................................................................................................................... 94 9.1.2 Model-view projection (MVP) transformation (OCCC coordinate transformation) ............. 95 9.1.3 3D-2D transformation (CCNDC coordinate transformation)............................................... 95 9.1.4 View port transformation (NDCDC coordinate transformation) .......................................... 96 9.1.5 View volume clipping.............................................................................................................. 96 9.1.6 Back face culling .................................................................................................................... 98 9.2 Data Format.................................................................................................................................. 99 9.2.1 Data format............................................................................................................................. 99 9.3 Setup Engine .............................................................................................................................. 100 9.3.1 Setup processing ................................................................................................................. 100 9.4 Log Output of Device Coordinates ............................................................................................. 100 9.4.1 Log output mode .................................................................................................................. 100 9.4.2 Log output destination address............................................................................................ 100 10.1 Coordinate System................................................................................................................... 101 10.1.1 Drawing coordinates .......................................................................................................... 101 10.1.2 Texture coordinates............................................................................................................ 102 10.1.3 Frame buffer....................................................................................................................... 102 10.2 Figure Drawing ......................................................................................................................... 103 10.2.1 Drawing primitives.............................................................................................................. 103 10.2.2 Polygon drawing function ................................................................................................... 103 10.2.3 Drawing parameters........................................................................................................... 104 10.2.4 Anti-aliasing function .......................................................................................................... 105 10.3 Bit Map Processing................................................................................................................... 106 10.3.1 BLT ..................................................................................................................................... 106 10.3.2 Pattern data format............................................................................................................. 106 10.4 Texture Mapping ....................................................................................................................... 107 94 101 MB86296S vi 11 DISPLAY LIST 10.4.1 Texture size ........................................................................................................................ 107 10.4.2 Texture color....................................................................................................................... 107 10.4.3 Texture Wrapping ............................................................................................................... 108 10.4.4 Filtering............................................................................................................................... 109 10.4.5 Perspective correction........................................................................................................ 109 10.4.6 Texture blending................................................................................................................. 110 10.4.7 Bi-linear high-speed mode ................................................................................................. 110 10.5 Rendering ................................................................................................................................. 112 10.5.1 Tiling ................................................................................................................................... 112 10.5.2 Alpha blending.................................................................................................................... 112 10.5.3 Logic operation................................................................................................................... 113 10.5.4 Hidden plane management................................................................................................ 113 10.6 Drawing Attributes .................................................................................................................... 114 10.6.1 Line drawing attributes ....................................................................................................... 114 10.6.2 Triangle drawing attributes ................................................................................................. 114 10.6.3 Texture attributes................................................................................................................ 115 10.6.4 BLT attributes ..................................................................................................................... 116 10.6.5 Character pattern drawing attributes.................................................................................. 116 10.7 Bold Line................................................................................................................................... 117 10.7.1 Starting and ending points.................................................................................................. 117 10.7.2 Broken line pattern ............................................................................................................. 118 10.7.3 Edging ................................................................................................................................ 119 10.7.4 Interpolation of bold line joint ............................................................................................. 120 10.8 Shadowing................................................................................................................................. 121 10.8.1 Shadowing........................................................................................................................... 121 11.1 Overview.................................................................................................................................... 122 11.1.1 Header format...................................................................................................................... 123 11.1.2 Parameter format................................................................................................................. 123 11.2 Geometry Commands................................................................................................................ 124 11.2.1 Geometry command list ...................................................................................................... 124 11.2.2 Explanation of geometry commands................................................................................... 128 11.3 Rendering Command................................................................................................................. 137 11.3.1 Command list....................................................................................................................... 137 11.3.2 Details of rendering commands........................................................................................... 141 122 12. PCI Configuration Registers 13 Local Memory Registers 12.1 PCI Configuration register list.................................................................................................... 151 12.2 PCI Configuration Registers Descriptions................................................................................. 152 13.1 Local memory register list ........................................................................................................ 155 13.1.1 Host interface register list................................................................................................... 155 13.1.2 I2C interface register list ..................................................................................................... 157 13.1.3 Graphics memory interface register list ............................................................................. 157 13.1.4 Display controller register list ............................................................................................. 158 13.1.5 Video capture register list................................................................................................... 165 13.1.6 Drawing engine register list................................................................................................ 167 13.1.7 Geometry engine register list ............................................................................................. 173 13.2 Explanation of Local Memory Registers................................................................................... 174 13.2.1 Host interface registers ...................................................................................................... 175 13.2.2 I2C Interface Registers ....................................................................................................... 190 151 155 MB86296S vii 14. TIMING DIAGRAM 13.2.3 Graphics memory interface registers ................................................................................. 196 13.2.4 Display control register....................................................................................................... 199 13.2.5 Video capture registers ...................................................................................................... 250 13.2.6 Drawing control registers ................................................................................................... 266 13.2.7 Drawing mode registers ..................................................................................................... 269 13.2.8 Triangle drawing registers .................................................................................................. 285 13.2.9 Line drawing registers ........................................................................................................ 288 13.2.10 Pixel drawing registers ..................................................................................................... 289 13.2.11 Rectangle drawing registers............................................................................................. 289 13.2.12 Blt registers ...................................................................................................................... 290 13.2.13 High-speed 2D line drawing registers .............................................................................. 291 13.2.14 High-speed 2D triangle drawing registers........................................................................ 292 13.2.15 Geometry control register................................................................................................. 293 13.2.16 Geometry mode registers................................................................................................. 295 13.2.17 Display list FIFO registers ................................................................................................ 302 15. ELECTRICAL CHARACTERISTICS 14.1 Host Interface ........................................................................................................................... 303 14.1.1 PCI Interface ...................................................................................................................... 303 14.1.2 EEPROM Timing ................................................................................................................ 304 14.1.3 Serial Interface Timing ....................................................................................................... 305 14.2 I2C Interface.............................................................................................................................. 306 14.3 Graphics Memory Interface ...................................................................................................... 307 14.3.1 Timing of read access to same row address...................................................................... 307 14.3.2 Timing of read access to different row addresses.............................................................. 308 14.3.3 Timing of write access to same row address ..................................................................... 309 14.3.4 Timing of write access to different row addresses ............................................................. 310 14.3.5 Timing of read/write access to same row address............................................................. 311 14.3.6 Delay between ACTV commands ...................................................................................... 312 14.3.7 Delay between Refresh command and next ACTV command........................................... 312 14.4 Display Timing .......................................................................................................................... 313 14.4.1 Non-interlace mode............................................................................................................ 313 14.4.2 Interlace video mode.......................................................................................................... 314 14.4.3 Composite synchronous signal .......................................................................................... 315 15.1 Introduction............................................................................................................................... 316 15.2 Maximum Rating....................................................................................................................... 316 15.3 Recommended Operating Conditions ...................................................................................... 317 15.3.1 Recommended operating conditions ................................................................................. 317 15.3.2 Note at power-on................................................................................................................ 318 Immediately after power-on, input clock to the PCLK pin for 10 clk or more. The XRST is taken in synchronizing with the PCLK............................................................................................................. 318 15.4 DC Characteristics.................................................................................................................... 319 15.4.1 DC Characteristics of PCI Buffer......................................................................................... 319 15.4.2 DC Characteristics of other than PCI buffer........................................................................ 321 15.5 AC Characteristics.................................................................................................................... 323 15.5.1 Host interface ..................................................................................................................... 323 15.5.2 I2C Interface ........................................................................................................................ 325 15.5.3 Video interface ................................................................................................................... 327 15.5.4 Video capture interface ....................................................................................................... 328 15.5.5 Graphics memory interface................................................................................................ 329 303 316 MB86296S viii 15.5.6 PLL specifications .............................................................................................................. 336 15.6 AC Characteristics Measuring Conditions................................................................................ 337 15.7 Timing Diagram ........................................................................................................................ 338 15.7.1 Host interface ..................................................................................................................... 338 15.7.2 Video interface ................................................................................................................... 339 15.7.3 Video capture interface ....................................................................................................... 340 15.7.4 Graphics memory interface................................................................................................ 341 MB86296S ix FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1. GENERAL 1.1 Preface The MB86296S MB86296S 1 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.2 Features * Geometry engine Geometry engine supports the geometry processing that is basically compatible**1 with ORCHID (MB86292). Using the display list created by ORCHID enables drawing. Heavy processing of geometric operations such as coordinates conversions or clipping performed by this device can reduce the CPU loads dramatically. **1(Floating point setup command is changed or deleted. G_BeginCont command is deleted. GMDR0 CF&DF table mapping is changed ... etc) 2D and 3D Drawing The MB86296 has a drawing function that is compatible with the CREMSON (MB86290A). It can draw data using the display list created for CREMSON. (But internal texture RAM is deleted.) The MB86296 also supports 3D rendering, such as texture mapping with perspective collection and Gouraud shading, alpha blending, and anti-aliasing for drawing smooth lines. Digital video capture The digital video capture function can store digital video data such as TV in graphics memory; it can display drawn images and video images on the same screen. Display controller The MB86296 has a display controller that is compatible with ORCHID. In addition to the traditional XGA (1024 x 768 pixels) display, 4-layer overlay, left/right split display, wrap-around scrolling, double buffers, and translucent display, function of 6-layer overlay, 4-siding for palette are expanded. Host CPU interface The MB86296 has a 32 bit, 33MHz PCI interface fully compliant to PCI version 2.1. External memory interface SDRAM and FCRAM can be connected. Optional function Final device can be selected from the combination of geometry high-/low-speed version and video capture function provided/ not provided. Others CMOS technology 0.18m BGA256 Package Supply voltage:1.8 V (internal operation) /3.3 V (I/O) Current consumption (TYPICAL) 1.8 V : 500mA 3.3 V : 100mA * * * * * * * MB86296S 2 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.3 Block Diagram CORAL-PA general block diagram is shown below: Pixel Bus PCI Bus AD0-31 Host Interface Capture Controller YUV/RGB Display Controller MD0-31/63 MA0-14 DRGB SDRAM or FCRAM External Memory Controller Geometry Engine 2D/3D Rendering Engine Fig.1.1 CORAL-PA Block Diagram MB86296S 3 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.4 Functional Overview 1.4.1 Host CPU interface Supported CPU Configuration PCI Slave The MB86296 can be connected to any CPU with a 33MHz 32-bit PCI v2.1 host interface. EEPROM configuration supported Serial interface for external device control through PCI interface Supports burst reads/writes of up to 8 double words (32 bytes). Supports multi-burst transfers with automatic pre-fetch. PCI Master Supports transfers of up to 224-1 double words in bursts of between 1 and 8 double words. Supports all combinations of transfer (PCI->PCI, PCI->Internal, Internal->PCI) Host notification on burst complete and/or transfer complete Optional external burst initiation control Internal DMA Interrupt Supports transfers of up to 224-1 double words in bursts of between 1 and 8 double words. Vertical (frame) synchronous detection Field synchronous detection External synchronous error detection Register update Drawing command error Drawing command execution end Burst/Transfer complete MB86296S 4 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.4.2 External memory interface SDRAM or FCRAM can be connected. 64 bits or 32 bits can be selected for data bus. Max. 133 MHz is available for operating frequency. Connectable memory configuration is as shown below. External Memory Configuration Type FCRAM 16 Mbits (x16 Bits) FCRAM 16 Mbits (x16 Bits) SDRAM 64 Mbits (x32 Bits) SDRAM 64 Mbits (x32 Bits) SDRAM 64 Mbits (x16 Bits) SDRAM 64 Mbits (x16 Bits) SDRAM 128 Mbits (x32 Bits) SDRAM 128 Mbits (x32 Bits) SDRAM 128 Mbits (x16 Bits) SDRAM 128 Mbits (x16 Bits) SDRAM 256 Mbits (x16 Bits) Data bus width 32 Bits 64 Bits 32 Bits 64 Bits 32 Bits 64 Bits 32 Bits 64 Bits 32 Bits 64 Bits 32 Bits Use count 2 4 1 2 2 4 1 2 2 4 2 Total capacity 4 Mbytes 8 Mbytes 8 Mbytes 16 Mbytes 16 Mbytes 32 Mbytes 16 Mbytes 32 Mbytes 32 Mbytes 64 Mbytes 64 Mbytes MB86296S 5 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.4.3 Display controller Video data output Screen resolution Analog RGB video output is provided. And each 8-bit digital video output is provided. When selecting each 8 bits output, usable external memory bus width is 32 bits only. LCD panels with wide range of resolutions are supported by using a programmable timing generator as follows: Screen Resolutions Resolutions 1024 x 768 1024 x 600 800 x 600 854 x 480 640 x 480 480 x 234 400 x 234 320 x 234 Hardware cursor MB8629x supports two hardware cursor functions. Each of these hardware cursors is specified as a 64 x 64-pixel area. Each pixel of these hardware cursors is 8 bits and uses the same look-up table as indirect color mode. Double buffer method in which drawing window and display window is switched in units of 1 frame enables the smooth animation. Flipping (switching of display window area) is performed in synchronization with the vertical blanking period using program. Independent setting of drawing and display windows and their starting position enables the smooth scrolling. Double buffer method Scroll method Display colors * * * * Supports indirect color mode which uses the look-up table (color palette) in 8 bits/pixels. Entry for look-up table (color palette) corresponds to color code for 8 bits, in other words, 256. Color data is each 6 bits of RGB. Consequently, 256 colors can be displayed out of 260,000 colors. Supports direct color mode which specifies RGB with 16 bits/pixels. Supports direct color mode which specifies RGB with 24 bits/pixels. MB86296S 6 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Overlay Compatibility mode Up to four extra layers (C, W, M and B) can be displayed overlaid. The overlay position for the hardware cursors is above/below the top layer (C). The transparent mode or the blend mode can be selected for overlay. The M- and B-layers can be split into separate windows. Window display can be performed for the W-layer. Two palettes are provided: C-layer and M-/B-layer. The W-layer is used as the video input layer. L0, L2, L4 (0,0) L1 (WX, WY) L3, L5 (HDB+1, 0) Window mode * * * * * * * * * Up to six screens (L0 to 5) can be displayed overlaid. The overlay sequence of the L0- to L5-layers can be changed arbitrarily. The overlay position for the hardware cursors is above/below the L0-layer. The transparent mode or the blend mode can be selected for overlay. The L5-layer can be used as the blend coefficient plane (8 bits/pixel). Window display can be performed for all layers. Four palettes corresponded to L0 to 3 are provided. The L1-layer is used as the video input layer. Background color display is supported in window display for all layers. L0 ( 0WX, L0WY) L L5 ( 5WX, L5WY) L L4 ( 4WX, L4WY) L2 ( 2WX, L2WY) L L L1 ( 1WX, L1WY) L L3 ( 3WX, L3WY) L MB86296S 7 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.4.4 Video capture function Video input * * The input format is either ITU RBT-656 or RGB666. Video data is stored in graphics memory once and then displayed on the screen in synchronization with the display scan. A scale-up factor 1 to 2 can be used. PAL or NTSC images can be displayed on a wide screen. A scale-down factor 1 to 1/32 can be used. Picture-in-picture can be used to display drawn images and video images on the same screen. Scaling * * * MB86296S 8 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.4.5 Geometry processing The MB86296 has a geometry engine for performing the numerical operations required for graphics processing. The geometry engine uses the floating-point format for highly precise operations. It selects the required geometry processing according to the set drawing mode and primitive type and executes processing to the final drawing. Primitives Point, line, line strip, independent triangle, triangle strip, triangle fan, and arbitrary polygon are supported. MVP Transformation Setting a 4 x 4 transformation matrix enables transformation of a 3D model view projection. Twodimensional affine transformation is also possible. MVP Transformation Clipping Culling Clipping stops drawing of figures outside the window (field of view). Polygons (including concave shapes) can also be clipped. Triangles on the back are not drawn. 3D-2D Transformation This functions transforms 3D coordinates (normalization) into 2D coordinates in orthogonal or perspective projections. This function transforms normalized 2D coordinates into drawing (device) coordinates. View port transformation Primitive setup This function automatically performs a variety of slope computations, etc., based on transforming vertex data into coordinates and prepares for rendering (setup). The view port conversion results are output to the local memory. Log output of device coordinates MB86296S 9 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.4.6 2D Drawing 2D Primitives MB8629x can perform 2D drawing for graphics memory (drawing plane) in direct color mode or indirect color mode. Bold lines with width and broken lines can be drawn. With anti-aliasing smooth diagonal lines also can be drawn. A triangle can be tiled in a single color or 2D pattern (tiling), or mapped with a texture pattern by specifying coordinates of the 2D pattern at each vertex (texture mapping). At texture mapping, drawing/non-drawing can be set in pixel units. Moreover, transparent processing can be performed using alpha blending. When drawing in single color or tiling without Gouraud shading or texture mapping, high-speed 2DLine and high-speed 2DTriangle can be used. Only vertex coordinates are set for these primitives. High-speed 2DTriangle is also used to draw polygons. 2D Primitives Primitive type Point Line Bold line strip (provisional name) Triangle High-speed 2DLine Arbitrary polygon Plots point Draws line Draws continuous bold line This primitive is used when interpolating the bold line joint. Draws triangle Draws lines Compared to line, this reduces the host CPU processing load. Draws arbitrary closed polygon containing concave shapes consisting of vertices Description Arbitrary polygon drawing Using this function, arbitrary closed polygon containing concave shapes consisting of vertices can be drawn. (There is no restriction on the count of vertices, however, the polygon with its sides crossed are not supported.) In this case, as a work area for drawing, polygon drawing flag buffer is used on the graphics memory. In drawing polygon, draw triangle for polygon drawing flag buffer using high-speed 2DTriangle. Decide any vertex as a starting point to draw triangle along the periphery. It enables you to draw final polygon form in single color or with tiling or with texture mapping in a drawing frame. MB86296S 10 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL BLT/Rectangle drawing This function draws a rectangle using logic operations. It is used to draw pattern and copy the image pattern within the drawing frame. It is also used for clearing drawing frame and Z buffer. BLT Attributes Attribute Raster operation Transparent processing Alpha blending Description Selects two source logical operation mode Performs BLT without drawing pixel consistent with the transparent color. The alpha map and source in the memory is subjected to alpha blending and then copied to the destination. Pattern (Text) drawing This function draws a binary pattern (text) in a specified color. Pattern (Text) Drawing Attributes Attribute Enlarge Shrink Description Vertically x 2 Horizontally x 2 Vertically and Horizontally x 2 Vertically x 1/2 Horizontally 1/2 Vertically and Horizontally 1/2 Drawing clipping This function sets a rectangle frame in drawing frame to prohibit the drawing of the outside the frame. MB86296S 11 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.4.7 3D Drawing 3D Primitives This function draws 3D objects in drawing memory in the direct color mode. 3D Primitives Primitive Point Line Triangle Arbitrary polygon Plots 3D point Draws 3D line Draws 3D triangle Draws arbitrary closed polygon containing concave shapes consisting of vertexes Description 3D Drawing attributes Texture mapping with bi-linear filtering/automatic perspective correction and Gouraud shading provides high-quality realistic 3D drawing. A built-in texture mapping unit performs fast pixel calculations. This unit also delivers color blending between the shading color and texture color. MB8629x supports the Z buffer for hidden plane management. Hidden plane management MB86296S 12 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1.4.8 Special effects Anti-aliasing Anti-aliasing manipulates line borders of polygons in sub-pixel units and blend the pre-drawing pixel color with color to make the jaggies be seen smooth. It is used as a functional option for 2D drawing (in direct color mode only). Bold line and broken line drawing This function draws lines of a specific width and a broken line. Line Drawing Attributes Attribute Line width Broken line * * * Description Selectable from 1 to 32 pixels Set by 32 bit or 24 bit of broken line pattern Supports the verticality of starting and ending points. Supports the verticality of broken line pattern. Interpolation of bold line joint supports the following modes: (1) Broken line pattern reference address fix mode The same broken line pattern is kept referencing for the period of some pixels starting from the joint and the starting point for the next line. (2) No interpolation Supports the equalization of the width of bold lines. Supports the bold line edging. Not support the Anti-aliasing of dashed line patterns. For a part overlaid due to connection of bold lines, natural overlay can be represented by providing depth information. (Z value). * * * * Shading Supports the shading primitive. Drawing is performed to the body primitive coordinates (X, Y) with an offset as a shade. At this drawing, the Z buffer is used in order to differentiate between the body and shade. MB86296S 13 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Alpha blending Alpha blending blends two image colors to provide a transparent effect. CORAL supports two types of blending; blending two different colors at drawing, and blending overlay planes at display. Transparent color is not used for these blending options. There are two ways of specifying alpha blending for drawing: (1) Set a transparent coefficient to the register; the transparent coefficient is applied for transparency processing of one plane. (2) Set a transparent coefficient for each vertex of the plane; as with Gouraud shading, the transparent coefficient is linear-interpolated to perform transparent processing in pixel units. In addition to the above, the following settings can be performed at texture mapping. When the most significant bit of each texture cell is 1, drawing or transparency can be set. When the most significant bit of each texture cell is 0, non-drawing can be set. Alpha Blending Type Drawing Description Overlay display Transparent ratio set in particular register While one primitive (polygon, pattern, etc.), being drawn, registered transparent ratio applied A transparent coefficient set for each vertex. A linearinterpolated transparent coefficient applied. This is possible only in direct color mode. Blends top layer pixel color with lower layer pixel color Transparent coefficient set in particular register Registered transparent coefficient applied during one frame scan Gouraud Shading Gouraud shading can be used in the direct color mode to provide 3D object real shading and color gradation. Gray Scale Gouraud Shading Gray scale gouraud shading can be used in the in-direct color mode to draw a blend coefficient layer. MB86296S 14 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Texture mapping MB86296 supports texture mapping to map a image pattern onto the surface of plane. For 2D pattern texture mapping, MB86296 has a built-in pattern memory for a field of up to 64 x 64 pixels (at 16-bit color), which performs high-speed texture mapping. The texture pattern can also be laid out in the graphics memory. In this case, max. 4096 x 4096 pixels can be used. Drawing of 8-/16-/24-bit direct color is supported for the texture pattern. For drawing 8-bit direct color, only point sampling can be specified for texture interpolation; only de-curl can be specified for the blend mode. Texture Mapping Function Filtering Blend Alpha blend Wrap Coordinates correction Description Point sample Bi-linear filter Linear Perspective De-curl Modulate Stencil Normal Stencil Stencil alpha Repeat Cramp Border 1.4.9 Others Direct color 24-bit direct color is supported in addition to 16-bit direct color as a drawing input data. The 24-bit direct color data is laid out on the memory by 32-bit-aligned. Top-left rule non-applicable mode In addition to the top-left rule applicable mode in which the triangle borders are compatible with CREMSON, the top-left rule non-applicable mode can be used. Caution: Use perspective correct mode when use texture at the top-left rule non-applicable mode. Top-left rule non-applicable primitives cannot use Geometry clip function. Non-top-left-part's pixel quality is less than body. (using approximate calculation) MB86296S 15 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2. PINS 2.1 Signals 2.1.1 Signal lines GPIO0-4 EEPROM0-4 AD0-31 CBE03 PAR FRAME TRDY IRDY STOP DEVSEL IDSEL PERR SERR REQ GNT PCLK XRST XINT BC TC BEN SB CORAL PA Graphics Controller BGA256 Host CPU interface DCLKO DCKLI HSYNC VSYNC CSYNC DISPE GV R2-7 G2-7 B2-7 XRGBEN MD0-63 MA0-14 MRAS MCAS MWE MDQM0-7 MCLKO MCLKI CCLK SDA SCL VI0-7 RI0-5 GI05 BI0-5 XRE RGBCLK COLSEL TESTH Video output interface Graphics memory interface Clock CLK S CKM CLKSEL0-1 Video capture interface Test Fig. 2.1 CORAL PA Signal Lines MB86296S FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.2 Pin Assignmen t 2.2.1 Pin assignment diagram INDEX 1 2 3 4 5 TOP VIEW 6 7 8 9 10 BGA256 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y NC VSYN GV BC COMR VRO COMG AVS GI3 GI4 DE GI0 GI2 DCKI AVS GI1 VS VH AOR VREF XTST DACT AOG AVD AOB AVD AVS VL MD60 MD59 VL MD57 MD54 MD53 MD50 MD46 MD44 MD41 MD38 VH VL VS SMCK CCLK MD61 MD56 AVD VS MST XSM MD49 MD45 MD42 MD40 MD35 MD34 DQM7 VH VL MD39 MD36 MD33 VS VS VH DQM4 MD62 MD55 MD52 MD48 MD63 MD58 MD51 VS XRE COMB MD43 MD47 MD37 MD32 DQM5 MRAS DQM6 MCAS MA12 VH MA6 MA4 MA0 VL REQ DCKO HSYN ECK RST EE PCLK VS VH AD27 EDO VS ECS EDI GNT CSYN XINT SB VH VL BEN VL VS TC VL MA11 MW E MA13 VL MA14 MA10 MA7 MA2 MA9 MA8 MA5 MA1 Thermal Balls In order to reduce heat, please connect to GND VS VL MA3 AD29 AD30 AD31 VH AD28 VS VL VS VL VH VS VS VS VH VS DQM2 MCKO DQM0 DQM3 VS VS MD23 VL VS DQM1 VH AD25 AD26 IDSL MD28 MD31 VL CBE3 AD24 VH MD29 MCKI AD22 AD23 MD27 MD21 MD25 MD30 MD16 MD18 MD22 MD26 VL VS VL VS VH VL AD02 PVD S PVS VS CSL1 VL CKM VL MD2 CSL0 CLK VH MD5 MD1 VS MD10 MD8 MD4 MD0 VS VH MD19 MD24 AD19 AD20 AD21 AD17 AD18 VH CBE2 AD16 DSEL SERR FRM VS IRDY STOP TRDY PERR PAR VH AD14 AD11 AD08 AD07 AD04 VH AD06 VH MD12 MD13 MD15 MD20 MD7 MD3 MD11 MD14 MD17 MD6 MD9 VS CBE1 AD13 AD10 AD15 AD12 AD09 CBE0 AD05 AD03 AD01 AD00 PCI Interface Pins Other Host I/f Pins Memory I/f Pins Muxed Memory I/f Pins DAC Pins Disp Pins Clock Pins Capture Pins Test Pins MB86296S 17 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.2.2 Pin assignment table JEDEC Number Pin Name B 2 GI3 C D E B E D C F E D G G D F E F H G F H J 2 3 4 1 3 2 1 3 2 4 4 3 1 2 1 4 3 2 1 2 4 GI4 DCKI VH VSYN HSYN DE GV CSYN DCKO VS VL SB BC EDO REQ XINT VH VS ECK ECS TC I/O Input Input Input I/O I/O Output Output Output Output I/O I/O I/O Output Output I/O I/O I/O Function RGB Input Green[3]. May also be configured as GPIO input. RGB Input Green[4]. May also be configured as GPIO input. Video output interface dot clock input. VDDH - 3.3V power supply. Video output interface vertical sync output. Vertical sync input in external sync mode. Video output interface horizontal sync output. Horizontal sync input in external sync mode. Video output interface display enable period. Video output interface graphics/video switch. Video output interface composite sync output. Video output interface dot clock signal for display. VSS - ground. VDDL 1.8V power supply. Host interface Slave Busy signal. May also be configured as GPIO input/output. In addition this signal is used as RGB input Green[5] and serial interface strobe depending on configuration. Host interface Burst Complete signal. May also be configured as GPIO input/output. In addition this signal is used as RGB input Red[0]. PCI configuration EEPROM data output. May also be configured as GPIO input/output. In addition this signal is used as RGB input Red[1] and serial interface data out depending on configuration. PCI request. External interrupt. By default (and PCI standard) it is active low. However it may be configured as active high if desired. VDDH 3.3V power supply. VSS - ground. PCI configuration EEPROM clock output. May also be configured as GPIO input/output. In addition this signal is used as RGB input Red[2] and serial interface clock out depending on configuration. PCI configuration EEPROM select output. May also be configured as GPIO input/output. In addition this signal is used as RGB input Red[3] depending on configuration. Host interface transfer complete. May also be configured as GPIO input/output. Note that the state of this pin is latched at external reset to help provide initial I/O configuration. If it is in an active high state then the EEPROM enable register bit is set. VDDL 1.8V power supply. Device reset. 18 (open drain) J G 3 1 VL XRST Input MB86296S FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL H J H K 4 2 1 3 VS EDI EE BEN K 2 GNT J 1 PCLK K 4 VL K 1 VS L 1 VH M 1 AD27 L 2 AD29 L 3 AD30 L 4 AD31 N 1 AD25 M 2 VH N 4 VS P 1 IDSL M 3 AD28 M 4 VL N 2 AD26 R 1 AD22 P 2 CBE3 N 3 VS R 4 VH T 1 AD19 R 2 AD23 P 3 AD24 U 1 AD17 P 4 VL Y 1 VS T 2 AD20 R 3 VH V 1 CBE2 U 2 AD18 T 3 AD21 W 1 FRM T 4 VS V 2 AD16 MB86296S VSS - ground. PCI configuration EEPROM data input. May also be configured as GPIO input/output. In addition this signal is used as RGB input Red[4] and serial interface data in depending on configuration. I/O PCI configuration EEPROM enable. May also be configured as GPIO input/output. In addition this signal is used as RGB input Red[5] depending on configuration. I/O Host interface burst enable used as an external trigger of the host interface burst controller. May also be configured as GPIO input/output. Note that the state of this pin is latched at external reset to help provide initial I/O configuration. If it is in an active high state then the RGB input enable register bit is set. Output PCI grant. Input PCI clock (33MHz). VDDL 1.8V power supply. VSS - ground. VDDH 3.3V power supply. I/O PCI address/data bit 27. I/O PCI address/data bit 29. I/O PCI address/data bit 30. I/O PCI address/data bit 31. I/O PCI address/data bit 25. VDDH 3.3V power supply. VSS - ground. Input PCI Initialisation Device Select (IDSEL). I/O PCI address/data bit 28. VDDL 1.8V power supply. I/O PCI address/data bit 26. I/O PCI address/data bit 22. I/O PCI command/byte enable 3. VSS - ground. VDDH 3.3V power supply. I/O PCI address/data bit 19. I/O PCI address/data bit 23. I/O PCI address/data bit 24. I/O PCI address/data bit 17. VDDL 1.8V power supply. VSS - ground. I/O PCI address/data bit 20. VDDH 3.3V power supply. I/O PCI command/byte enable 2. I/O PCI address/data bit 18. I/O PCI address/data bit 21. I/O PCI Frame. VSS - ground. I/O PCI address/data bit 16. 19 I/O FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL U V W W V U Y V W Y V W U U V Y W Y U V W Y W U V Y U W Y V W Y U Y Y Y W V U Y 3 3 2 3 4 5 2 5 4 3 6 5 4 7 7 4 6 5 6 8 7 6 8 9 9 7 8 9 8 10 10 9 10 10 11 12 11 11 11 13 VH DSEL IRDY STOP SERR VS TRDY VH PAR PERR AD14 CBE1 VS VL AD11 VH AD13 AD15 VS AD08 AD10 AD12 VH VL AD07 AD09 VS AD06 CBE0 AD04 VH AD05 VS AD03 AD01 AD00 AD02 VL VH CKM (open drain) I/O I/O I/O Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input VDDH 3.3V power supply. PCI Device Select (DEVSEL). PCI Initiator Ready. PCI Stop. PCI System Error. VSS - ground. PCI Target Ready. VDDH 3.3V power supply. PCI Parity. PCI Parity Error. PCI address/data bit 14. PCI command/byte enable 1. VSS - ground. VDDL 1.8V power supply. PCI address/data bit 11. VDDH 3.3V power supply. PCI address/data bit 13. PCI address/data bit 15. VSS - ground. PCI address/data bit 8. PCI address/data bit 10. PCI address/data bit 12. VDDH 3.3V power supply. VDDL 1.8V power supply. PCI address/data bit 7. PCI address/data bit 9. VSS - ground. PCI address/data bit 6. PCI command/byte enable 0. PCI address/data bit 4. VDDH 3.3V power supply. PCI address/data bit 5. VSS - ground. PCI address/data bit 3. PCI address/data bit 1. PCI address/data bit 0. PCI address/data bit 2. VDDL 1.8V power supply. VDDH 3.3V power supply. Clock Mode. If low then the output from the internal PLL is used as the internal clock. If high then the PCI clock is used. PLL Ground. VSS - ground. Clock input. PLL reset. PLL 1.8V power supply. VDDL 1.8V power supply. 20 W 12 PVS U 13 VS Y 14 CLK V 12 S U 12 PVD W 13 VL MB86296S Input Input - FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Y 15 VS W 14 CSL0 V 13 CSL1 U 15 VH Y 16 MD0 W 15 MD1 V 14 MD2 Y 17 MD3 U 14 VL Y 20 VS W 16 MD4 V 15 MD5 Y 18 MD6 W 17 MD7 V 16 MD8 Y 19 MD9 U 16 MD10 W 18 MD11 V 17 MD12 V 18 MD13 W 19 MD14 V 19 MD15 U 18 VH T 17 MD16 W 20 MD17 T 18 MD18 U 19 MD19 V 20 MD20 R 18 MD21 T 19 MD22 U 17 VS P 17 MD23 P 18 VL U 20 MD24 R 19 MD25 T 20 MD26 R 17 MD27 N 18 MD28 P 19 MD29 R 20 MD30 N 19 MD31 M 17 VS M 18 VL P 20 MCKI N 17 VS M 19 VS N 20 VH L 18 MCKO MB86296S Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Output VSS - ground. Clock rate selection 0. Clock rate selection 1. VDDH 3.3V power supply. Graphics memory data bit 0. Graphics memory data bit 1. Graphics memory data bit 2. Graphics memory data bit 3. VDDL 1.8V power supply. VSS - ground. Graphics memory data bit 4. Graphics memory data bit 5. Graphics memory data bit 6. Graphics memory data bit 7. Graphics memory data bit 8. Graphics memory data bit 9. Graphics memory data bit 10. Graphics memory data bit 11. Graphics memory data bit 12. Graphics memory data bit 13. Graphics memory data bit 14. Graphics memory data bit 15. VDDH 3.3V power supply. Graphics memory data bit 16. Graphics memory data bit 17. Graphics memory data bit 18. Graphics memory data bit 19. Graphics memory data bit 20. Graphics memory data bit 21. Graphics memory data bit 22. VSS - ground. Graphics memory data bit 23. VDDL 1.8V power supply. Graphics memory data bit 24. Graphics memory data bit 25. Graphics memory data bit 26. Graphics memory data bit 27. Graphics memory data bit 28. Graphics memory data bit 29. Graphics memory data bit 30. Graphics memory data bit 31. VSS - ground. VDDL 1.8V power supply. Graphics memory clock input. VSS - ground. VSS - ground. VDDH 3.3V power supply. Graphics memory clock output. 21 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L M L L K J K K K H J H G J J H F G H F E F G D G A E F C D E B E C D C B B C D A 19 20 17 20 20 20 19 18 17 20 19 17 20 18 17 19 20 19 18 17 20 19 18 20 17 20 19 18 20 19 18 20 17 19 18 18 19 18 17 16 19 DQ0 M DQM1 DQM2 DQM3 VL MA0 MA1 MA2 MA3 MA4 MA5 VS MA6 MA7 VL MA8 VH MA9 MA10 MA11 MA12 MA13 MA14 MRAS VL VS MCAS MWE DQM4 DQM5 DQM6 DQM7 VS VH MD32 MD33 MD34 MD35 MD36 MD37 MD38 Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output MB86296S Graphics memory data mask 0. Graphics memory data mask 1. Graphics memory data mask 2. Graphics memory data mask 3. VDDL 1.8V power supply. Graphics memory address bit 0. Graphics memory address bit 1. Graphics memory address bit 2. Graphics memory address bit 3. Graphics memory address bit 4. Graphics memory address bit 5. VSS - ground. Graphics memory address bit 6. Graphics memory address bit 7. VDDL 1.8V power supply. Graphics memory address bit 8. VDDH 3.3V power supply. Graphics memory address bit 9. Graphics memory address bit 10. Graphics memory address bit 11. Graphics memory address bit 12. Graphics memory address bit 13. Graphics memory address bit 14. Graphics memory row address strobe. VDDL 1.8V power supply. VSS - ground. Graphics memory column address strobe. Graphics memory write enable. Graphics memory data mask 4. Graphics memory data mask 5. Graphics memory data mask 6. May also be configured as Blue[0] for the RGB output. Output Graphics memory data mask 7. May also be configured as Blue[1] for the RGB output. VSS - ground. VDDH 3.3V power supply. I/O Graphics memory data bit 32. May also be configured as Blue[2] for the RGB output. I/O Graphics memory data bit 32. May also be configured as Blue[3] for the RGB output. I/O Graphics memory data bit 32. May also be configured as Blue[4] for the RGB output. I/O Graphics memory data bit 32. May also be configured as Blue[5] for the RGB output. I/O Graphics memory data bit 32. May also be configured as Blue[6] for the RGB output. I/O Graphics memory data bit 32. May also be configured as Blue[7] for the RGB output. I/O Graphics memory data bit 32. May also be configured as Green[0] for the RGB output. 22 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL C B A C B D D C A B A D C B A B D C A D B A C B A D 16 17 18 15 16 17 14 14 17 15 16 15 13 14 15 13 12 12 14 13 12 13 11 11 12 11 MD39 MD40 MD41 VL MD42 VS MD43 VH MD44 MD45 MD46 MD47 MD48 MD49 MD50 VL MD51 MD52 MD53 VS VH MD54 MD55 MD56 MD57 MD58 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O MB86296S Graphics memory data bit 32. May also be configured as Green[1] for the RGB output. Graphics memory data bit 32. May also be configured as Green[2] for the RGB output. Graphics memory data bit 32. May also be configured as Green[3] for the RGB output. VDDL 1.8V power supply. Graphics memory data bit 32. May also be configured as Green[4] for the RGB output. VSS - ground. Graphics memory data bit 32. May also be configured as Green[5] for the RGB output. VDDH 3.3V power supply. Graphics memory data bit 32. May also be configured as Green[6] for the RGB output. Graphics memory data bit 32. May also be configured as Green[7] for the RGB output. Graphics memory data bit 32. May also be configured as Red[0] for the RGB output.R0 Graphics memory data bit 32. May also be configured as Red[1] for the RGB output.R1 Graphics memory data bit 32. May also be configured as Red[2] for the RGB output.R2 Graphics memory data bit 32. May also be configured as Red[3] for the RGB output.R3 Graphics memory data bit 32. May also be configured as Red[4] for the RGB output.R4 VDDL 1.8V power supply. Graphics memory data bit 51. May also be configured as Red[5] for the RGB output.R5 Graphics memory data bit 52. May also be configured as Red[6] for the RGB output.R6 Graphics memory data bit 53. May also be configured as Red[7] for the RGB output. R7 VSS - ground. VDDH 3.3V power supply. Graphics memory data bit 54. May also be configured as I2C serial data (SDA). Graphics memory data bit 55. May also be configured as I2C serial clock (SCL). Graphics memory data bit 56. May also be configured as ITU-RBT-656 video capture data input bit 0 (VI0). When the RGB input is enabled this pin acts as Blue[0]. Graphics memory data bit 57. May also be configured as ITU-RBT-656 video capture data input bit 1 (VI1). When the RGB input is enabled this pin acts as Blue[1]. Graphics memory data bit 58. May also be configured as ITU-RBT-656 video capture data input bit 2 (VI2). When the RGB input is enabled this pin acts as Blue[2]. 23 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL A A A B C D A B D A C D B A B C D A B C A D A B C A B C A D B C C 11 10 9 10 10 10 8 9 8 7 9 9 8 6 7 8 6 5 6 7 4 7 1 5 6 3 4 5 2 5 3 4 3 VL MD59 MD60 MD61 MD62 MD63 VL CCLK VS DACT MST XSM SMCK XTST AOB AVD2 COMB AVS2 AOG AVD1 COMG AVS1 NC AOR AVD0 VRO AVS0 VREF COMR XRE GI0 GI1 GI2 I/O I/O I/O I/O I/O Input Input Input Input Input Input Output Output Output Output Output Output Input Output Input GI0 GI1 GI2 MB86296S VDDL 1.8V power supply. Graphics memory data bit 59. May also be configured as ITU-RBT-656 video capture data input bit 3 (VI3). When the RGB input is enabled this pin acts as Blue[3]. Graphics memory data bit 60. May also be configured as ITU-RBT-656 video capture data input bit 4 (VI4). When the RGB input is enabled this pin acts as Blue[4]. Graphics memory data bit 61. May also be configured as ITU-RBT-656 video capture data input bit 5 (VI5). When the RGB input is enabled this pin acts as Blue[5]. Graphics memory data bit 62. May also be configured as ITU-RBT-656 video capture data input bit 6 (VI6). When the RGB input is enabled this pin acts as HSYNC. Graphics memory data bit 63. May also be configured as ITU-RBT-656 video capture data input bit 7 (VI7). When the RGB input is enabled this pin acts as VSYNC. VDDL 1.8V power supply. ITU-RBT-656 video capture clock input. VSS - ground. Test signal. Test signal. Test Signal. Test Signal. Test Signal. Analog Signal (B) output Analog Power Supply(3.3V) Analog B Signal Compensation pin Analog Ground Analog Singnal (G) output Analog Power Supply(3.3V) Analog G Signal Compensation pin Analog Ground Not connected. Analog Singnal (R) output Analog Power Supply(3.3V) Analog Reference current output Analog Ground Analog Reference Voltage input Analog R Signal Compensation pin RGB output/video input/I2C enable. RGB Input Green[0]. May also be configured as GPIO input. RGB Input Green[1]. May also be configured as GPIO input. RGB Input Green[2]. May also be configured as GPIO input. 24 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Notes VSS/PLLVSS VDDH VDDL/PLLVDD PLLVDD OPEN TESTH AVS AVD : : : : : : : : Ground 3.3-V power supply 1.8-V power supply PLL power supply (1.8 V) Do not connect anything. Input a 3.3 V-power supply. Analog Ground Analog power supply (3.3 V) - It is recommended that PLLVDD should be isolated on the PCB. - It is recommended that AVD should be isolated on the PCB. - Insert a bypass capacitor with good high frequency characteristics between the power supply and ground. Place the capacitor as near as possible to the pin. MB86296S 25 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.3 Pin Function 2.3.1 Host CPU interface Table 2-1 Host CPU Interface Pins Pin name AD0-31 CBE0-3 PAR FRM TRDY IRDY STOP DSEL IDSEL PERR SERR REQ GNT PCLK XRST XINT BC I/O In/Out In/Out In/Out In/Out In/Out In/Out In/Out In/Out Input In/Out Output (Open Drain) Output Input Input Input Output (Open Drain) Output Description PCI Address/Data PCI Bus Command/Byte Enable PCI Parity PCI Cycle Frame PCI Target Ready PCI Initiator Ready PCI Stop PCI Device Select PCI Initialisation Device Select PCI Parity Error System Error PCI Bus Master Request PCI Bus Grant PCI Clock - 33MHz System Reset (including PCI) Interrupt Burst Complete. Indicates a burst is complete when using the DMA/Burst Controller. This pin may also be configured as a GPIO Input/Output and acts as RI0 (Red Input 0) when the RGB Input is enabled. Transfer Complete. Indicates that a whole transfer is complete when using the DMA/Burst Controller. This may also be configured as a GPIO Input/Output. In addition this pin may be used to automatically enable the EEPROM at the reset phase. To do this a pull up should be applied. Enables the Burst Controller to start/continue execution. This pin may also be configured as a GPIO Input/Output. In addition this pin may be used to automatically enable the RGB Input pins as RGB inputs. To do this a pull up should be applied. Slave Busy. Indicates that the PCI Slave is busy completing a write transfer. This pin may also be configured as a GPIO Input/Output, the Serial Interface Strobe Output and acts as GI5 (Green Input 5) when the RGB Input is enabled. TC Output BEN Input SB Output MB86296S 26 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL EE ECS ECK EDO EDI GI0-4 Input Output Output Output Input Input EEPROM Enable. Enables the PCI EEPROM Configuration. This pin may also be configured as a GPIO Input/Output and acts as RI5 (Red Input 5) when the RGB Input is enabled. EEPROM Chip Select . This pin may also be configured as a GPIO Input/Output and acts as RI3 (Red Input 3) when the RGB Input is enabled. EEPROM Clock. This pin may also be configured as a GPIO Input/Output, the Serial Interface clock Output and acts as RI2 (Red Input 2) when the RGB Input is enabled. EEPROM Data Out. This pin may also be configured as a GPIO Input/Output, the Serial Interface Data Output and acts as RI1 (Red Input 1) when the RGB Input is enabled. EEPROM Data In. This pin may also be configured as a GPIO Input/Output, the Serial Interface Data Input and acts as RI4 (Red Input 4) when the RGB Input is enabled. GPIO Inputs. These pins also act as GI0-4 (Green Inputs 04) when the RGB Input is enabled. The EE, ECK, ECS, EDO, EDI, BC, TC, SB and BEN signals can all be configured as GPIO inputs/outputs and default to GPIO inputs at reset unless otherwise specified by the reset control pins (TC, BEN) which can be used to enable the EEPROM or the RGB input. The GI0-4 signals can be GPIO inputs only, which is their default state unless the RGB input is enabled in which case they are used as Green[0-4]. The Host Interface also has a serial interface function built in. This uses the EDI/EDO signals as data in/out, the ECK pin as a serial clock output and the SB pin as a strobe output. The serial interface may only be used when neither the EEPROM nor the RGB input is in use. Once the device has been reset all configuration of the host interface related pins is done using the IO Mode register (IOM). Note that to enable the RGB input the XRE signal must be active low and also the appropriate register in the capture engine must be configured. MB86296S 27 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.3.2 Video output interface Table 2-2 Video Output Interface Pins DCKO DCKI HSYN VSYN CSYN DE GV R7-0 G7-0 B7-0 XRE AOR AOG AOB COMR COMG COMB VREF VRO Pin name Output Input I/O I/O Output Output Output Output Output Output Input I/O Analog Output Analog Output Analog Output Analog Analog Analog Analog Analog Dot clock signal for display Dot clock signal input Horizontal sync signal output Horizontal sync input Description It is possible to output digital RGB when XRE = 0 (Memory bus = 32bit). Additional setting of external circuits can generate composite video signal. Synchronous to external video signal display can be performed. Either mode which is synchronous to DCLKI signal or one which is synchronous to dot clock, as for normal display can be selected. Since HSYNC and VSYNC signals are set to input state after reset, these signals must be pulled up LSI externally. The GV signal switches graphics and video at chroma key operation. When video is selected, the "Low" level is output. AOR, AOG and AOB must be terminated at 75 ohm. 1.1 V is input to VREF. A bypass capacitor ( with good high-frequency characteristics ) must be inserted between VREF and AVS. COMR, COMG and COMB are tied to analog VDD via 0.1 uF ceramic capacitors. VRO must be pulled down to analog ground by a 2.7 k ohm resister. When not using DAC, it is possible to connect all of analog pins(AVD, AOUTR,G,B, ACOMPR,G,B, VREF, VRO) to GND. MB86296S 28 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL The 16bit/pixel color mode and 8bit/pixel color mode are converted to digital R:G:B=8:8:8 as the below. A) 16bit/pixel color mode R:G:B=5:5:5 data in graphics memory 0 1-31 B) 8bit/pixel color mode Digital R:G:B=8:8:8 0 Add 11 to lower 2bits Formula=X*4+3 The Y,Cb,Cr mode is converted to R:G:B=8:8:8 directly. R:G:B=6:6:6 data in color palette 0 1-63 Digital R:G:B=8:8:8 0 Add 111 to lower 3bits Formula=X*8+7 MB86296S 29 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.3.3 Video capture interface 1. ITU-656 Input Signals Table 2-3 Video Capture Interface Pins CCLK VI7-0 Pin name Input Input I/O Digital video input clock signal input ITU656 Digital video data input. These pins are multiplexed MD63MD56. Description Inputs ITU-RBT-656 format digital video signal Digital video data input can be used only when the XRE pin is "0". MD63-MD56 are assigned as the digital video data input pins. When video capture is not used and the XRE pin is 0, input the "High" level to MD63-MD56. 2. RGB Input Signals Direct Input Mode Pin name RGBCLK RI5-0 GI5-0 BI5-0 VSYNCI HSYNCI The signals used for video capture are not assigned on dedicated pins but share the same pins with other functions. There is a set of signals corresponding to the RGB capture modes. I/O Description Input Input Input Input Input Input Clock for RGB input. This pin is multiplexed CCLK. Red component value. These pins are multiplexed EE, EDI, ECS, ECK, EDO and BC. Green component value. These pins are multiplexed SB and GPI4GPI0. Blue component value. These pins are multiplexed MD61-MD56. Vertical sync for RGB capture. This pin is multiplexed MD63. Horizontal sync for RGB capture. This pin is multiplexed MD62. Note : - the RGB bit of VCM(video capture mode) register enables RGB input mode of video capture. MB86296S 30 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.3.4 I2C interface Pin name SDA SCL I/O I/O I/O I2C or Video capture test signal. This pin is multiplexed MD54. I2C or Video capture test signal. This pin is multiplexed MD55. Description I2C interface signals can be used only when the XRE pin is "0". MD55-MD54 are assigned as the I2C interface pins. When I2C interface is not used and the XRE pin is 0, input the "High" level to MD63-MD56. Note) Input voltage level is 3.3V. Please be careful, it does not support to 5V input. (The device whose output voltage is 5V is not connectable.) MB86296S 31 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.3.5 Graphics memory interface Graphics memory interface pins Pin name MD31 - MD0 MD53 - MD32 MD55 - MD54 MD63 - MD56 MA0 to 14 MRAS MCAS MWE DQM5 - DQM0 DQM7 - DQM6 MCLK0 MCLK1 I/O I/O I/O I/O Output Output Output Output Output Output Output Input I/O Description Graphics memory bus data Graphics memory bus data or digital R7-0, G7-0, B7-2 output (when XRE = 0) Graphics memory bus data or SCL, SDA (when XRE=0) Graphics memory bus data or video input (when XRE=0) Graphics memory bus data Row address strobe Column address strobe Write enable Data mask Data mask or digital B1-0 output (when XRE = 0) Graphics memory clock output Graphics memory clock input Connect the interface to the external memory used as memory for image data. The interface can be connected to 64-/128-/256-Mbit SD RAM (16- or 32-bit length data bus) without using any external circuit. 64 bits or 32 bits can be selected for the memory bus data. . Connect MCLKI to MCLK0. When XRE is fixed at "1", MD63 - MD32 and DQM7 - DQM6 can be used as graphics memory interface. When XRE is fixed at "0", these signals can be used as digital RGB output and digital video data input. MB86296S 32 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.3.6 Clock input Table 2-4 Clock Input Pins Pin name CLK S CKM CSL [1:0] I/O Input Input Input Input Description Clock input signal PLL reset signal Clock mode signal Clock rate select signal Inputs source clock for internal operation clock and display dot clock. Normally, 4 Fsc (= 14.31818 MHz: NTSC) is input. An internal PLL generates the internal operation clock of 166 MHz/133 MHz and the display base clock of 400 MHz. Even if don't use an internal PLL (use BCLKI as internal clock and use DCLKI as dot clock), don't stop the PLL (Not fixed the S pin to low level). CKM L H * Clock mode Output from internal PLL selected PCI bus clock selected When CKM = L, selects input clock frequency when built-in PLL used according to setting of CSL pins CSL1 L L H H L H L H CSL0 Input clock frequency Inputs 13.5-MHz clock frequency Inputs 14.32-MHz clock frequency Inputs 17.73-MHz clock frequency Inputs 33.33-MHz clock frequency Multiplication rate x 29 x 28 x 22 x 12 Display reference clock 391.5 MHz 400.96 MHz 390.06 MHz 399.96 Please connect the crystal oscillator directly with the terminal CLK. MB86296S 33 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2.3.7 Test pins Table 2-5 Test Pins Pin name TESTH I/O Input Input 3.3-V power. Description 2.3.8 Reset sequence See Section 15.3.2. 2.3.9 How to switch internal operating frequency * * Switch the operating frequency immediately after a reset (before rewriting MMR mode register of external memory interface). Any operating frequency can be selected from the five combinations shown in Table 2-6. Table 2-6 Frequency Setting Combinations Clock for geometry engine 166 MHz 166 MHz 133 MHz 133 MHz 100 MHz * Clock for other than geometry engine 133 MHz 100 MHz 133 MHz 100 MHz 100 MHz The following relationship is disabled: Clock for geometry engine < Clock for other than geometry engine MB86296S 34 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 3. PROCEDURE OF THE HARDWARE INITIALIZATION 3.1. Hardware reset 1.Do the hardware reset. (see section 15.3.2) 2.After the hardware reset, set the CCF(Change of Frequency) register (section 13.2.1). In being unstable cycle after the hardware reset, keep 32 bus cycles open. 3. Turn OFF a pre-fetch function. Set the TRC (HostBase+00b8h) register. Please set 0x00000002 (bit1 set 1 and other set 0). 4.Set the graphics memory interface register, MMR (Memory I/F Mode Register). After setting the CCF register, take 200 us to set the MMR register. In being unstable memory access cycle, keep 32 bus cycles open. 5.Other registers, except for the CCF register and the MMR register, should be set after setting the CCF register. In case of not using memory access, the MMR register could be set in any order after the CCF register is set. 3.2. Re-reset 1. Reset XRST signal. 2. See section 3.1 for registers setting after the procedure of re-reset. 3.3. Software reset 1. Set the value of the SRST register (see section 13.2.1) for re-reset. 2. It is not necessary to reset the CCF register and the MMR register again. MB86296S 35 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 4. HOST INTERFACE The Coral PA has a 33MHz, 32-bit PCI host interface compliant to PCI version 2.1. It includes both PCI master and PCI slave functions and an internal DMA/burst controller for multi-burst transfers of large quantities of data between all combinations of PCI data space and Coral PA internal data space. PCI EEPROM configuration is also supported. Additional functions provided by the host interface are optional host interface status/control signals which may aid in the reduction of PCI retries, the provision of general purpose IO (GPIO) signals for control of external devices via the PCI interface including support for a simple serial interface. 4.1 Standard PCI Slave Accesses An external PCI master will access the Coral PA as a PCI slave. 4.1.1 PCI Slave Write For a PCI slave write, data will be "posted" into a temporary buffer from where it is written to the target internal client. This temporary buffer is 8 dwords deep. PCI slave writes of any size are supported but typically a retry will occur after each 8 dword burst. Note that when writing to the display list FIFO a burst should be no more than 16 dwords (64 bytes) due to FIFO address space limitations. When the write from the temporary buffer to the internal client is being performed the Slave Busy (SB) signal becomes active. While this is happening PCI accesses will be rejected. If the SB signal is used then PCI retries may be reduced. 4.1.2 PCI Slave Read For a PCI slave read the read requested will be passed to an internal client from where data will be fetched into the temporary buffer (8 dwords deep). Typically a retry will occur to actually fetch the data. In order to fetch the correct number of words from the read address the burst size must be specified. This is done by writing to the Slave Burst Read Size (SRBS) register. Bursts of between 1 and 8 dwords are supported. If the PCI master retries and reads less than the specified burst size then the remaining dwords will be discarded. This means that the Slave Burst Read Size can be permanently configured as 8 dwords. However there will be an increased latency on the pre-fetch stage if this is done. When data is transmitted in large quantities from a graphics memory, Please set 0x00000000 to TRC(HostBase+00b8h) before using this function. The pre-fetch function is turned ON and improves transfer rate. Please set the pre-fetch function as OFF according to the procedure of the explanation part of a TRC register after slave burst READ to the last graphic memory. 4.2 Burst Controller Accesses (including PCI Master) The Coral PA host interface includes a burst controller which can be used for transferring large quantities of contiguous data between all combinations (source/destination) of PCI data space and Coral PA internal data space. Control/status monitoring is done through internal registers with the optional aid of external signals - Burst Complete (BC), Transfer Complete (TC) and Burst Enable (BEN). MB86296S 36 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL A transfer can be any number of dwords from 1 to 16777215 (224-1) dwords, split up into a number of individual bursts of size from 1 to 8 dwords. If the transfer size is not an integer multiple of the burst size then the final burst of the transfer will be less than the configured burst size. A transfer is from a source address to a destination address with the source/destination being in either PCI or Coral PA data space as appropriate to the transfer mode. After each burst of a transfer the source and/or the destination address may be incremented (or not) by the burst size enabling transfers both to/from memory and also FIFO-like sources/destinations. Note that when writing to the display list FIFO, the destination address should be configured to not increment between bursts. 4.2.1 Transfer Modes There are 6 transfer modes configurable through the Burst Setup Register (BSR). These are: Mode 000b Function Slave Mode PCI to Coral PA. In this mode a PCI master writes bursts of data directly into a temporary buffer from where it is transferred to the destination address by the Burst Controller. While this can also be accomplished using simple PCI Slave writes there are benefits in using this mode when transferring large quantities of data. For a normal PCI write the Coral PA PCI slave interface is blocked until the write to the destination address has completed. Depending on the destination there may be some delay in doing this. Using the burst controller the data is transferred out of the PCI interface into the temporary buffer from where it is transferred to the destination. In this case the PCI slave interface is quickly cleared and so other operations can take place or the next burst can be written in. Slave Mode Coral PA to PCI. In this mode the burst controller reads data from a Coral PA internal address into its temporary buffer and then waits for the data to be read using a PCI slave read from this buffer's address. While this can also be accomplished using simple PCI Slave reads there are benefits in using this mode when transferring large quantities of data. A normal PCI read will typically be accomplished by a PCI read request followed by a retry to fetch the data. Using this mode the burst controller can be used to automatically fetch the next data to be read. Depending on internal latencies this should reduce the number of retries. Coral PA to Coral PA. In this mode data is read from a source address internal to Coral PA into a temporary buffer, from where it is written to a destination, also internal to Coral PA. An example of where this mode may be used is to transfer display list data from graphics memory to the display list FIFO. Reserved. PCI to Coral PA (PCI Master read). In this mode the source address is in PCI data space and the destination address internal to Coral PA. For each burst of the transfer "burst size" dwords of data are read as a PCI Master read into a temporary buffer, from where they are written to the internal destination address. An example of where this mode will be used is display list transfer to the FIFO/graphics memory. Coral PA to PCI (PCI Master write). In this mode the source address is internal to Coral PA and the destination address is in PCI data space. For each burst of the transfer "burst size" dwords of data are fetched from an internal address into a temporary buffer, from where they are written to the destination address using a PCI master write. An example of where this mode may be used is to transfer graphics memory data to external PCI memory. 001b 010b 011b 100b 101b MB86296S 37 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 110b 111b PCI to PCI (PCI Master read/write). This mode is effectively a PCI to PCI DMA. Data is read from a source address in PCI data space into a temporary buffer from where it is written to the destination address, also in PCI data space. Reserved. The figure below illustrates a PCI to Coral (Master Read) transfer. The Host CPU will program up the BCU registers (using normal PCI Slave writes) and trigger the transfer. The Coral then reads data from the source memory as a PCI Master and writes to the destination inside the Coral. Memory (PCI Slave) Coral PA 2) Master Read from source PCI Bus RAM 3) Onward transfer to destination BCU Internal Bus Host CPU (PCI Master) 1) Slave Write to setup transfer All other BCU transfers use the BCU RAM in a similar way but with source/destination dependent on transfer type. 4.2.2 Burst Controller Control/Status All setup/control and status for the burst controller can be done through registers. These provide ways of specifying the parameters for a burst (source/destination address, address increment (or not) and burst/transfer size. In addition, a transfer can be started/paused/aborted and also its progress monitored using the enable and status registers. The key status indicators are Burst Complete and Transfer Complete, which become active at the end of each burst/transfer respectively. These may either be active high or toggle state at the end of each burst/transfer. When active high they will have to be cleared after each burst/transfer. This may be done using a clear on read mode (default) or by manually writing to the appropriate register. The burst/transfer complete indications are also available though the main interrupt status register (IST) and can trigger the main external interrupt (XINT). If being used for this they must be configured as active high (ie. not toggle mode). In addition burst/transfer complete can be made available as external signals (BC/TC) for connection directly to an external device (eg. through some form of GPIO or interrupt). Normally a transfer will be configured and enabled using internal registers. However it is possible to configure the transfer but not actually start it. An external signal (BEN) can then be used to trigger the MB86296S 38 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL transfer and pause it between bursts. This may be useful, for example, when doing PCI Master reads from a client which takes time to pre-fetch more data for the next burst. 4.3 FIFO Transfers Unlike Coral LQ/Coral LB there are no specific transfer mechanisms to write data into the display list FIFO. A write to the FIFO interface occurs automatically when it is specified as a destination address either for a PCI Slave Write or in a Burst Controller transfer. If this is not desired, and the main internal bus should be used, then the Override FIFO Use register may be set. Under normal circumstances there should be no need to use this feature. As previously stated when the FIFO address is specified as the destination in the Burst Controller the destination should not be incremented after each burst. This will not happen automatically and must be specifically configured. In addition when writing to the FIFO using a PCI Slave Write the FIFO address space is limited to 16 dwords (64 bytes). This means that a PCI Slave Write burst to the FIFO must not be more than 16 dwords, otherwise data will be written to invalid locations for retries after 2 bursts of 8 dwords. In normal mode when writing to the FIFO, data is written to the Geometry Engine FIFO from where it is transferred either directly to the Draw Engine FIFO or to the Geometry Engine, depending on the command. If the Geometry Engine is not in use then a direct write to the Draw Engine FIFO can be accomplished by setting Cremson Mode (CM register). When the burst controller is used to transfer data to the FIFO the rate of bursts us controlled using the current FIFO status. When the FIFO is nearly full the next burst will not occur until data is processed by the Geometry/Draw Engine. This guarantees that there will always be space for the next burst of data. If this feature is not required then it can be disabled using the FIFO Burst Mode (FBM) register. 4.4 GPIO/Serial Interface The Host Interface supports optional register mapped General Purpose IO (GPIO) and Serial Interface functions. 4.4.1 GPIO Depending on configuration there are up to 14 GPIO signals. 5 of these (GI0, GI1, GI2, GI3, GI4) are inputs only. The remainder (BEN,SB,TC,BC,EE,ECS,ECK,EDI, EDO) may be either input or output. All reset to GPIO inputs unless otherwise configured using the reset configuration mechanism to enable the EEPROM/RGB input. Operation of the GPIO is simply through the reading of the GPIO Data (GD) register for GPIO Inputs and writing to this register (with write mask) for the GPIO Outputs. GPIO Inputs may be configured selectively to trigger an external interrupt (via the interrupt status register (IST)) when they change state (0->1 or 1->0 transition). 4.4.2 Serial Interface A simple serial interface is available depending on configuration. This uses the EDI/EDO pins as serial data input/output, the ECK as the serial clock output and SB as the serial interface strobe. The serial data out signal may be tri-stated when not in use. Up to 8 bits of data is shifted out/in based on the serial clock. This may be 1/16, 1/32, 1/64 or 1/128 of the main internal clock. The clock polarity may be specified to be high/low and it may be gated when the serial interface is inactive. MB86296S 39 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL The strobe signal has configurable polarity and may be active only for the first cycle of a transfer or the complete transfer. It may also be disabled completely. Configured strobe settings may be overridden on a transfer by transfer basis if required. An interrupt may be generated when a transfer is complete. 4.5 Interrupt The Coral PA MB86296 issues interrupt requests to the host CPU. The following interrupt triggers may enabled/disabled using the Interrupt Mask Register (IMASK). * * * * * * * * * * * * * Vertical synchronization detect Field synchronization detect External synchronization error detect Register update Drawing command error Drawing command execution end Internal Bus/FIFO Timeout Serial Interface transfer complete GPIO input change Burst Complete Transfer Complete Host Interface Fatal (PCI error) Address Error (invalid address accessed) In addition the I2C interface can trigger an interrupt, but this is non-maskable through the IMASK register. By default the external interrupt is active low (PCI standard) and is open drain. If required it may be configured to be active high using the Interrupt Polarity (IP) register. Once an interrupt is detected by the host it can read the interrupt status register (IST) to determine the source of the interrupt. The exception to this is the I2C interrupt. Once read the interrupt status register must be cleared by writing 0 to the appropriate bit/bits (selective clearing is possible). Note that the Burst Complete/Transfer Complete interrupts must be cleared by writing to the Burst Status (BST) register. 4.5.1 Address Error Interrupt Certain addresses are invalid depending on operation. For example the Burst Controller cannot access the Host Interface internal registers. If an attempt is made to do this then the access will be terminated and an Address Error Interrupt triggered. MB86296S 40 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 4.6 Memory Map The local memory base address of Coral-PA is determined by Memory Base Address Register 0 (PCI Byte Address=0x10) in PCI Configuration Registers. The following shows the local memory map of Coral PA to the host CPU memory space. 64 MB Space Graphics memory area Register area 32 MB to 256 KB 256 KB 0000000 to 1FBFFFF 1FC0000 to 1FFFFFF 32 MB Graphics memory area 2000000 to 3FFFFFF Fig. 3.1 Memory Map Table 3-4 Address Space Size 32 MB to 256 KB 64 KB 32 KB 32 KB 64 KB 32 KB 32 KB 32 MB Resource Graphics Memory Host interface registers (I2C interface registers) Display registers Video capture registers Internal texture memory Drawing registers Geometry engine registers Graphics memory Base address 00000000 01FC0000 (01FCC000) 01FD0000 01FD8000 01FE0000 01FF0000 01FF8000 02000000 (Name) (HostBase) (I2CBase) (DisplayBase) (CaptureBase) (TextureBase) (DrawBase) (GeometryBase) MB86296S 41 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL If required the register area can be moved by writing 1 to bit 0 at HostBase + 005Ch (RSW: Register location Switch). In the initial state, the register space is at the center (1FC0000) of the 64 MB space. Coral PA may be accessed after about 20 bus clocks after writing 1 to RSW. 64 MB space 32 MB Graphics memory area 0000000 to 1FFFFFF 32 MB to 256 KB Graphics memory area Register area 2000000 to 3FBFFFF 256 KB 3FC0000 to 3FFFFFF Fig. 3.2 Alternate Memory Map Table 3-5 Alternate Address Mapping Size 64 MB to 256 KB 64 KB 32 KB 32 KB 64 KB 32 KB 32 KB Resource Graphics memory Host interface registers (I2C interface registers) Display registers Video capture registers Internal texture memory Drawing registers Geometry engine registers Base address 00000000 03FC0000 (03FCC000) 03FD0000 03FD8000 03FE0000 0 3FF0000 03FF8000 (Name) (HostBase) (I2CBase) (DisplayBase) (CaptureBase) (TextureBase) (DrawBase) (GeometryBase) MB86296S 42 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5. I 2C Interface Controller 5.1 Features - Master transmission and receipt - Slave transmission and receipt - Arbitration - Clock synchronization - Detection of slave address - Detection of general call address - Detection of transfer direction - Repeated generation and detection of START condition - Detection of bus error - Correspondence to standard-mode (100kbit/s ) / high-speed-mode (400kbit/s) MB86296S 43 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5.2 Block diagram 5.2.1 Block Diagram SDA SCL noise filter START condition/STOP condition detecting circuit ADR Comparater Host Bus Host IF DAR BSR BCR CCR Arbitration Lost detecting circuit START condition/STOP condition generating circuit Shift Clock generating circuit I2C UNIT MB86296S 44 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5.2.2 Block Function Overview START condition / STOP condition detecting circuit This circuit performs detection of START condition and STOP condition from the state of SDA and SCL. This circuit performs generation of START condition and STOP condition by changing the state of SDA and SCL. START condition / STOP condition generating circuit Arbitration Lost detecting circuit This circuit compares the data output to SDA line with the data input into SDA line at the time of data transmission, and it checks whether these data is in agreement. When not in agreement, it generates arbitration lost. Shift Clock generating circuit Comparater ADR This circuit performs generating timing count of the clock for serial data transfer, and output control of SCL clock by setup of a clock control register. Comparater compares whether the received address and the self-address appointed to be the address register is in agreement, and whether the received address is a global address. ADR is the 7-bit register which appoints a slave address. DAR BSR DAR is the 8-bit register used by serial data transfer. BSR is the 8-bit register for the state of I2C bus etc. This register has following functions: - detection of repeated START condition - detection of arbitration lost - storage of acknowledge bit - data transfer direction - detection of addressing - detection of general call address - detection of the 1st byte BCR is the 8-bit register which performs control and interruption of I2C bus. This register has following functions: - request / permission of interruption - generation of START condition - selection of master / slave - permission to generate acknowledge BCR MB86296S 45 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL CCR CCR is the 7-bit register used by serial data transfer. This register has following functions: - permission of operation - setup of a serial clock frequency - selection of standard-mode / high-speed-mode Noise filter This noise filter consists of a 3 step shift register. When all three value that carried out the continuation sampling of the SCL/SDA input signals is "1", the filter output is "1". Conversely when all three value is "0", the filter output is "0". To other samplings it holds the state before 1 clock. 5.3 Example application 5.3.1 Connection Diagram 3.3V Slave Device SDA SCL SDA SCL MB86296S 46 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5.4 Function overview Two bi-directional buses, serial data line (SDA) and serial clock line (SCL), carry information at I2Cbus. Scarlet I2C interface has SDA input (SDAI) and SDA output (SDAO) for SDA and is connected to SDA line via open-drain I/O cell. And this interface also has SCL input (SCLI) and SCL output (SCLO) for SCL line and is connected to SCL line via open-drain I/O cell. The wired theory is used when the interface is connected to SDA line and SCL line. 5.4.1 START condition If "1" is written to MSS bit while the bus is free, this module will become a master mode and will generate START condition simultaneously. In a master mode, even if a bus is in a use state (BB=1), START condition can be generated again by writing "1" to SCC bit. There are two conditions to generate START condition. - "1" writing to MSS bit in the state where the bus is not used (MSS=0 & BB=0 & INT=0 & AL=0) - "1" writing to SCC bit in the interruption state in a master mode (MSS=1 & BB=1 & INT=1 & AL=0) If "1" writing is performed to MSS bit in an idol state, AL bit will be set to "1". "1" writing to MSS bit other than the above is disregarded. SDA SCL START condition 5.4.2 STOP condition If "0" is written to MSS bit in a master mode (MSS=1), this module will generate STOP condition and will become a slave mode. There is a condition to generate STOP condition. - "0" writing to MSS bit in the interruption state in a master mode (MSS=1 & BB=1 & INT=1 & AL=0) "0" writing to MSS bit other than the above is disregarded. SDA SCL STOP condition MB86296S 47 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL In a master mode, it is set to BB="1" and TRX="0" after generation of START condition, and the contents of DAR register are output from MSB. When this module receives acknowledge after transmission of address data, the bit-0 of transmitting data (bit-0 of DRA register after transmission) is reversed and it is stored in TRX bit. 5.4.3 Addressing - Transfer format of slave address A transfer format of slave address is shown below: MSB A6 A5 A4 A3 slave address A2 A1 A0 LSB R/W ACK - Map of slave address A map of slave address is shown below: slave address 0000 000 0000 000 0000 001 0000 010 0000 011 0 0 0 0 1XX 0 0 0 1 XXX 1 1 1 0 XXX 1 1 1 1 0 XX 1 1 1 1 1 XX R/W 0 1 X X X X X X X Description General call address START byte CBUS address Reserved Reserved Reserved Available slave address 10-bit slave addressing*1 Reserved *1 This module does not support 10-bit slave address. 5.4.4 Synchronization of SCL When two or more I2C devices turn into a master device almost simultaneously and drive SCL line, each devices senses the state of SCL line and adjusts the drive timing of SCL line automatically in accordance with the timing of the latest device. MB86296S ----- 48 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL When other masters have transmitted data simultaneously at the time of master transmission, arbitration takes places. When its own transmitting data is "1" and the data on SDA line is "0", the master considers that the arbitration was lost and sets "1" to AL. And if the master is going to generate START condition while the bus is in use by other master, it will consider that arbitration was lost and will set "1" to AL. When the START condition which other masters generated is detected by the time the master actually generated START condition, even when it checked the bus is in nonuse state and wrote in MSS="1", it considers that the arbitration was lost and sets "1" to AL. When AL bit is set to "1", a master will set MSS="0" and TRX= "0" and it will be a slave receiving mode. When the arbitration is lost (it has no royalty of a bus), a master stops a drive of SDA. However, a drive of SCL is not stopped until 1 byte transfer is completed and interruption is cleared. 5.4.5 Arbitration 5.4.6 Acknowledge Acknowledge is transmitted from a reception side to a transmission side. At the time of data reception, acknowledge is stored in LRB bit by ACK bit. When the acknowledge from a master reception side is not received at the time of slave transmission, it sets TRX="0" and becomes slave receiving mode. Thereby, a master can generate STOP condition when a slave opens SCL. 5.4.7 Bus error When the following conditions are satisfied, it is judged as a bus error, and this interface will be in a stop state. - Detection of the basic regulation violation on I2C-bus under data transfer (including ACK bit) - Detection of STOP condition in a master mode - Detection of the basic regulation violation on I2C-bus at the time of bus idol SDA D7 D6 D5 SCL START 1 2 3 SDA changed under data transmission (SCL=H). It becomes bus error. MB86296S 49 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5.4.8 Initialize Start ADR: write CCR: write CS[4:0]: write EN: 1write setup of slave address setup of clock frequency setup of macro enable BCR: write BER: 0write BEIE: 1write INT: 0write INTE: 1write setup of interruption End MB86296S 50 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5.4.9 1-byte transfer from master to slave master DAR: write MSS: 1write BB set,TRX set Start slave START condition BB set,TRX reset Transfer of address data AAS set LRB reset INT set, TRX set DAR: write INT: 0write Acknowledge INT set,TRX reset ACK: 1write INT: 0write Interruption data transfer LRB reset INT set acknowledge INT set DAR: read INT: 0write BB reset,TRX reset AAS reset interruption MSS: 0write INT reset BB reset, TRX reset STOP condition End MB86296S 51 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5.4.10 1-byte transfer from slave to master master DAR:write MSS:1write BB set , T RX set Start slave START condition BB set, TRX reset Transfer of address data AAS set LRB reset INT set, TRX set ACK: 0write INT: 0write Acknowledge INT set, TRX reset DAR: write INT: 0write Iterruption Data transfer Negative acknowledge LRB set, RTX set IN T set INT set DAR: read MSS: 0write INT reset BB reset, TRX reset Interruption INT: 0write BB reset, TRX reset AAS reset STOP condition End MB86296S 52 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5.4.11 Recovery from bus error Start BCR: write BER: 0write BEIE: 1write CCR: write CS[4:0]: write EN: 1write Cancellation of error flag Setup of clock frequency Setup of macro enable BCR: write BER: 0write BEIE: 1write INT: 0write INTE: 1write Setup of interruption End MB86296S 53 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5.5 Note A ) About a 10-bit slave address This module does not support the 10-bit slave address. Therefore, please do not specify the slave address of from 78H to 7bH to this module. If it is specified by mistake, a normal transfer cannot be performed although acknowledge bit is returned at the time of 1 byte reception. Competition of the following byte transfer, generation of START condition, and generation of STOP condition happens by the simultaneous writing of SCC, MSS, and INT bit. At this time the priority is as follows. 1) The following byte transfer and generation of STOP condition If "0" is written to INT bit and "0" is written to MSS bit, priority will be given to "0" writing to MSS bit and STOP condition will be generated. 2) The following byte transfer and generation of START condition If "0" is written to INT bit and "1" is written to SCC bit, priority will be given to "1" writing to SCC bit and START condition will be generated. 3) Generation of START condition and generation of STOP condition The simultaneous writing of "1" in SCC bit and "0" to MSS bit is prohibition. When the delay of the positive edge of SCL terminal is large or when the clock is extended by the slave device, it may become smaller than setting value (calculation value) because of generation of overhead. B ) About competition of SCC, MSS, and INT bit C ) About setup of S serial transfer clock MB86296S 54 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 6. Graphics Memory 6.1. Configuration The Coral uses local external memory (Graphics memory) for drawing and display management. The configuration of this Graphics memory is described as follows: 6.1.1. Data type The Coral handles the following types of data. Display list can be stored in the host (main) memory as well. Texture/tile pattern and text pattern can be defined by a display list as well. Drawing Frame This is a rectangular image data field for 2D/3D drawing. The Coral is able to have plural drawing frames and display a part of these area if it is set to be bigger than display size. The maximum size is 4096x4096 pixel in 32 pixel units. And both indirect color ( 8 bits / pixel) and direct color ( 16 bits / pixel) mode are applicable. Display Frame Z Buffer This is a rectangle picture area for display. The Coral is able to set display layer up to 6 layers. Z buffer is required for eliminating hidden surfaces. In 16 bits modes, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. This area has to be cleared before drawing. Polygon Drawing Flag Buffer This area is used for polygon drawing. It is required 1 bit memory area per 1 pixel and 1 x-axis line area both backward and forward of it. This area has to be cleared before drawing. Frame buffer, Z buffer, Displaylist and etc By XRES size Base Address of Polygon Drawing Buffer(PFBR) By drawing frame sizy By XRES size Frame buffer, Z buffer, Displaylist and etc Polygon drawing flag area => (Y resolution + 2) * X resolution Displaylist Buffer Texture Pattern Cursor Pattern The displaylist is a list of drawing commands and parameters. This pattern is used for texture mapping. The maximum size is up to 4096 x 4096 pixels. This is used for hardware cursor. The data format is indirect color ( 8 bits / pixel) mode. And the Coral is able to display two cursor of 64 x 64 pixel size. MB86296S 55 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 6.1.2. Memory Mapping A graphics memory is mapped linearly to host CPU address field. Each of these above data is able to be allocated anywhere in the Graphics memory according to the respective register setting. ( However there is some restrictions of an addressing boundary depending on a data type.) 6.1.3. Data Format Direct Color ( 16 bits / pixel ) 15 This data format is described RGB as each 5 bit. Bit15 is used for alpha bit of layer blending. A 14 13 12 R 11 10 9 8 G 7 6 5 4 3 B 2 1 0 This data format is a color index code for looking up table (palette). 7 6 5 Indirect Color ( 8 bits / pixel ) 4 Color Code 3 2 1 0 Z Value 15 It is possible to use Z value as 8 bits or 16 bits. These data format are unsigned integer. 1 ) 16 bits mode 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unsigned Integer 1 0 2 ) 8 bits mode 7 6 5 Unsigned Integer 4 3 2 This data format is 1 bit per 1 pixel. P15 P14 P13 P12 P11 P10 P9 31 30 29 28 27 26 15 14 13 12 11 10 9 Polygon Drawing Flag P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 25 P8 8 24 P7 7 23 P6 6 22 P5 5 21 P4 4 20 P3 3 19 P2 18 2 P1 17 1 P0 16 0 MB86296S 56 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL It is possible to use a pattern as direct color mode ( 16 bits / pixel) or indirect color mode ( 8 bits / pixel). 1 ) Direct color mode ( 16 bits / pixel) This data format is described RGB as each 5 bit. Bit15 is used for alpha bit of stencil or stencil blending. ( Only texture mapping) 15 Texture / Tile Pattern A 14 13 12 R 11 10 9 8 G 7 6 5 4 3 B 2 1 0 2) Indirect color mode ( 8 bits / pixel) This data format is a color index code for looking up table (palette). 7 6 5 Color Code 4 3 2 1 0 This data format is a color index code for looking up table (palette). 7 6 5 Cursor Pattern Color Code 4 3 2 1 0 This data format is Y:Cb:Cr=4:2:2 and 32 bits per 2 pixel. 15 31 14 30 13 29 12 28 Video Capture data Y0 Y1 11 27 10 26 9 25 8 24 7 23 6 22 5 21 4 20 Cb Cr 3 19 2 18 1 17 0 16 This data format is described RGB as each 8 bit. Bit31 is used for alpha bit of layer blending. But the Coral does not support this color mode drawing. Therefore please draw this layer by CPU writing. 15 31 14 30 13 29 12 28 Direct Color ( 32 bits / pixel ) G 11 27 10 26 9 25 8 24 7 23 6 22 5 21 4 20 B R 3 19 2 18 1 17 0 16 A Reserved MB86296S 57 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 6.2. Frame Management 6.2.1. Single Buffer The entire or partial area of the drawing frame is assigned as a display frame. The display field is scrolled by relocating the position of the display frame. When the display frame crosses the border of the drawing frame, the other side of the drawing frame is displayed, assuming that the drawing frame is rolled over (top and left edges assumed logically connected to bottom and right edges, respectively). To avoid the affect of drawing on display, the drawing data can be transferred to the Graphics Memory in the blanking time period. 6.2.2. Double Buffer Two drawing frames are set. While one frame is displayed, drawing is done at the other frame. Flicker-less animation can be performed by flipping these two frames back and forth. Flipping is done in the blanking time period. There are two flipping modes: automatically at every scan frame period, and by user control. The double buffer is assigned independently for the L2, L3, L4, L5 layers. 6.3. Memory Access 6.3.1. Memory Access by host CPU Graphics memory is mapped linearly to host CPU address field. The host CPU can access the Graphics memory like a SRAM. 6.3.2. Priority of memory accessing 1. 2. 3. 4. 5. Refresh Video Capture Display processing Host CPU accessing Drawing accessing The priority of Graphics memory accessing is the follows: MB86296S 58 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 6.4. Connection with memory 6.4.1. Connection with memory The memory controller of Coral supports simple connection with SD/FCRAM by setting MMR(Memory Mode Register). If there is N(=11 to 13) address pins in SD/FCRAM, please connect the SD/FCRAM address(A[n]) pin to the Coral's memory address(MA[n]) pin and SD/FCRAM bank pin to the Coral's next address(MA[N]) pin. Then please set MMR by a number and type of memory. The follows are the connection table between Coral pin and SD/FCRAM pin. Coral pins MA[11:0] MA12 MA13 64M bit SDRAM(x16 bit) SDRAM pins A[11:0] BA0 BA1 SDRAM pins A[11:0] BA0 BA1 SDRAM pins A[12:0] BA0 BA1 64M bit SDRAM(x32 bit) Coral pins MA[10:0] MA11 MA12 SDRAM pins A[10:0] BA0 BA1 SDRAM pins A[11:0] BA0 BA1 FCRAM pins A[10:0] BA Coral pins MA[11:0] MA12 MA13 Coral pins MA[12:0] MA13 MA14 128M bit SDRAM(x16 bit) 128M bit SDRAM(x32 bit) Coral pins MA[11:0] MA12 MA13 Coral pins MA[10:0] MA11 256M bit SDRAM(x16 bit) 16M bit FCRAM(x16 bit) MB86296S 59 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7. DISPLAY CONTROLLER 7.1 Overview Display control Window display can be performed for six layers. Window scrolling, etc., can also be performed. Backward compatibility with previous products is supported in the four-layer display mode or in the left/right split display mode. Backward compatibility Video timing generator Color look-up Cursor The video display timing is generated according to the display resolution (from 320 x 240 to 1024 x 768). There are two sets of color look-up tables by palette RAM for the indirect color mode (8 bits/pixel). Two sets of hardware cursor patterns (8 bits/pixel, 64 x 64 pixels each) can be used. MB86296S 60 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.2 Display Function 7.2.1 Layer configuration Six-layer window display is performed. Layer overlay sequence can be set in any order. A four-layer display mode and left/right split display mode are also provided, supporting backward compatibility with previous products. L0 (L0WX,L0WY) L5 (L5WX,L5WY) L4 (L4WX,L4WY) L2 (L2WX,L2WY) L1 (L1WX,L1WY) L0,L2,L4 (0,0) L1 (WX,WY) L3,L5 (HDB+1,0) L3 (L3WX,L3WY) background color (a) Six layerd window display (b) Four layered display for downward compatibility Configuration of Display Layers The correspondence between the display layers for this product and for previous products is shown below. Coordinates of starting point Width/height Layer correspondence Window mode Compatibility Window mode Compatibility mode mode L0 L1 L2 L3 L4 L5 C W ML MR BL BR (L0WX, L0WY) (L1WX, L1WY) (L2WX, L2WY) (L3WX, L3WY) (L4WX, L4WY) (L5WX, L5WY) (0, 0) (WX, WY) (0, 0) (HDB, 0) (0, 0) (HDB, 0) (L0WW, L0WH + 1) (L1WW, L1WH + 1) (L2WW, L2WH + 1) (L3WW, L3WH + 1) (L4WW, L4WH + 1) (L5WW, L5WH + 1) (HDP + 1, VDP + 1) (WW, WH + 1) (HDB + 1, VDP + 1) (HDP - HDB, VDP + 1) (HDB + 1, VDP + 1) (HDP - HDB, VDP + 1) C, W, ML, MR, BL, and BR above mean layers for previous products. The window mode or the compatibility mode can be selected for each layer. It is possible to use new functions through minor program changes by allowing the coexistence of display modes instead of separating them completely. However, if high resolutions are displayed, the count of layers that can be displayed simultaneously and pixel data may be restricted according to the graphics memory ability to supply data. MB86296S 61 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.2.2 Overlay (1) Overview Image data for the six layers (L0 to L5) is processed as shown below. L0(C) data Cursor0 data Cursor1 data L1(W) data L2(ML) data L3(MR) data L4(BL) data L5(BR) data L2 data L3 data L4 data L5 data Pallet-0 Overlay Pallet-1 Layer Selector YUV/RGB Pallet-2 Pallet-3 The fundamental flow is: Palette Layer selection Blending. The palettes convert 8-bit color codes to the RGB format. The layer selector exchanges the layer overlay sequence arbitrarily. The blender performs blending using the blend coefficient defined for each layer or overlays in accordance with the transparent-color definition. The L0 layer corresponds to the C layer for previous products and shares the palettes with the cursor. As a result, the L0 layer and cursor are overlaid before blend operation. The L1 layer corresponds to the W layer for previous products. To implement backward compatibility with previous products, the L1 layer and lower layers are overlaid before blend operation. The L2 to L5 layers have two paths; in one path, these layers are input to the blender separately and in the other, these layers and the L1 layer are overlaid and then are input to the blender. When performing processing using the extended mode, select the former; when performing the same processing as previous products, select the latter. It is possible to specify which one to select for each layer. MB86296S 62 Blender FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL (2) Overlay mode Image layer overlay is performed in two modes: simple priority mode, and blend mode. In the simple priority mode, processing is performed according to the transparent color defined for each layer. When the color is a transparent color, the value of the lower layer is used as the image value for the next stage; when the color is not a transparent color, the value of the layer is used as the image value for the next stage. Dview = Dnew (when Dnew does not match transparent color) = Dlower (when Dnew matches transparent color) When the L1 layer is in the YCbCr mode, transparent color checking is not performed for the L1 layer; processing is always performed assuming that transparent color is not used. In the blend mode, the blend ratio "r" defined for each layer is specified using 8-bit tolerance, and the following operation is performed: Dview = Dnew*r + Dlower*(1 - r) Blending is enabled for each layer by mode setting and a specific bit of the pixel is set to "1". For 8 bits/pixel, the MSB of RAM data enables blending; for 16 bits/pixel, the MSB of data of the relevant layer enables blending; for 24 bits/pixel, the MSB of the word enables blending. (3) Blend coefficient layer In the normal blend mode, the blend coefficient is fixed for each layer. However, in the blend coefficient layer mode, the L5 layer can be used as the blend coefficient layer. In this mode, the blend coefficient can be specified for each pixel, providing gradation, for example. When using this mode, set the L5 layer to 8 bits/pixel, widow display mode and extend overlay mode. MB86296S 63 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.2.3 Display parameters The display area is defined according to the following parameters. independently at the respective register. HSP HDP HDB LnWY VDP LnWX LnWW LnWH HTP HSW Each parameter is set VTR VSW VSP Fig. 5.1 Display Parameters Note: The actual parameter settings are little different from the above. The details, please refer "14.3.1 Interlaced mode". HTP HSP HSW HDP HDB VTR VSP VSW VDP LnWX LnWY LnWW LnWH Horizontal Total Pixels Horizontal Synchronize pulse Position Horizontal Synchronize pulse Width Horizontal Display Period Horizontal Display Boundary Vertical Total Raster Vertical Synchronize pulse Position Vertical Synchronize pulse Width Vertical Display Period Layer n Window position X Layer n Window position Y Layer n Window Width Layer n Window Height When not splitting the window, set HDP to HDB and display only the left side of the window. The settings must meet the following relationship: 0 < HDB HDP < HSP < HSP + HSW + 1 < HTP 0 < VDP < VSP < VSP + VSW + 1 < VTR MB86296S 64 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.2.4 Display position control The graphic image data to be displayed is located in the logical 2D coordinates space (logical graphics space) in the Graphics Memory. There are six logical graphics spaces as follows: * * * * * * L0 layer L1 layer L2 layer L3 layer L4 layer L5 layer The relation between the logical graphics space and display position is defined as follows: Origin Address (OA) Stride (W) Display Address (DA) Display Position X,Y (DX,DY) Logical Frame Height (H) VDP Display Frame HDP Fig. 5.2 Display Position Parameters OA W H DA DX DY Origin Address Stride Height Display Address Display Position Origin address of logical graphics space. Memory address of top left edge pixel in logical frame origin Width of logical graphics space. Defined in 64-byte unit Height of logical graphics space. Total raster (pixel) count of field Display origin address. Top left position address of display frame origin Display origin coordinates. Coordinates in logical framespace of display frame origin MB86296S 65 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL MB8629x scans the logical graphics space as if the entire space is rolled over in both the horizontal and vertical directions. Using this function, if the display frame crosses the border of the logical graphics space, the part outside the border is covered with the other side of the logical graphics space, which is assumed to be connected cyclically as shown below: Logical Frame Origin 64 w Previous display origin New display origin L Additionally drawn area Fig. 5.3 Wrap Around of Display Frame The expression of the X and Y coordinates in the frame and their corresponding linear addresses (in bytes) is shown below. A(x,y) = x x bpp/8 + 64wy (bpp = 8 or 16) The origin of the displayed coordinates has to be within the frame. To be more specific, the parameters are subject to the following constraints: 0 DX < w x 64 x 8/bpp (bpp = 8 or 16) 0 DY < H DX, DY, and DA have to indicate the same point within the frame. In short, the following relationship must be satisfied. DA = OA + DX x bpp/8 + 64w x DY (bpp = 8 or 16) MB86296S 66 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.3 Display Color Color data is displayed in the following modes: Indirect color (8 bits/pixel) Direct color (16 bits/pixel) Direct color (24 bits/pixel) In this mode, the index of the palette RAM is displayed. Data is converted to image data consisting of 6 bits for R, G, and B via the palette RAM and is then displayed. Each level of R, G, and B is represented using 5 bits. Each level of R, G, and B is represented using 8 bits. YCbCr color (16 bits/pixel) In this mode, image data is displayed with YCbCr = 4:2:2. Data is converted to image data consisting of 8 bits for R, G, and B using the operation circuit and isthen displayed. The display colors for each layer are shown below. Layer L0 L1 L2 L3 L4 L5 Direct color (16, 24), Indirect color (P0) Direct color (16, 24), Indirect color (P1), YCbCr Direct color (16, 24), Indirect color (P1) Direct color (16, 24), Indirect color (P1) Direct color (16, 24), Indirect color (P1) Direct color (16, 24), Indirect color (P1) Compatibility mode Direct color (16, 24), Indirect color (P0) Direct color (16, 24), Indirect color (P1), YCbCr Direct color (16, 24), Indirect color (P2) Direct color (16, 24), Indirect color (P3) Direct color (16, 24) Direct color (16, 24) Extended mode "Pn" stands for the corresponding palette RAM. Four palettes are used as follows: Palette 0 (P0) Palette 1 (P1) This palette corresponds to the C-layer palette for previous products. This palette is used for the L0 layer. This palette can also be used for the cursor. This palette corresponds to the M/B layer palette for previous products. In the compatibility mode, this palette is common to layers L1 to 5. In the extended mode, this palette is dedicated to the L1 layer. Palette 2 (P2) Palette 3 (P3) This palette is dedicated to the L2 layer. This palette can be used only for the extended mode. This palette is dedicated to the L3 layer. This palette can be used only for the extended mode. MB86296S 67 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.4 Cursor 7.4.1 Cursor display function CORAL can display two hardware cursors. Each cursor is specified as 64 x 64 pixels, and the cursor pattern is set in the Graphics Memory. The indirect color mode (8 bits/pixel) is used and the L0 layer palette is used. However, transparent color control (handling of transparent color code and code 0) is independent of L0 layer. Blending with lower layer is not performed. 7.4.2 Cursor control The display priority for hardware cursors is programmable. The cursor can be displayed either on upper or lower the L0 layer using this feature. A separate setting can be made for each hardware cursor. If part of a hardware cursor crosses the display frame border, the part outside the border is not shown. Usually, cursor 0 is preferred to cursor 1. However, with cursor 1 displayed upper the L0 layer and cursor 0 displayed lower the L0 layer, the cursor 1 display is preferred to the cursor 0. MB86296S 68 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.5 Display Scan Control 7.5.1 Applicable display The following table shows typical display resolutions and their synchronous signal frequencies. The pixel clock frequency is determined by setting the division rate of the display reference clock. The display reference clock is either the internal PLL (400.9 MHz at input frequency of 14.318 MHz), or the clock supplied to the DCLKI input pin. The following table gives the clock division rate used when the internal PLL is the display reference clock: Table 4-1 Resolution and Display Frequency Resolution 320 x 240 400 x 240 480 x 240 640 x 480 854 x 480 800 x 600 1024 x 768 Division rate of reference clock 1/60 1/48 1/40 1/16 1/12 1/10 1/6 Horizontal Horizontal Vertical Pixel Vertical frequency total pixel frequency total raster frequency count count 6.7 MHz 8.4 MHz 10.0 MHz 25.1 MHz 33.4 MHz 40.1 MHz 66.8 MHz 424 530 636 800 1062 1056 1389 15.76 kHz 15.76 kHz 15.76 kHz 31.5 kHz 31.3 kHz 38.0 kHz 48.1 kHz 263 263 263 525 525 633 806 59.9 Hz 59.9 Hz 59.9 Hz 59.7 Hz 59.9 Hz 60.0 Hz 59.9 Hz Pixel frequency = 14.318 MHz x 28 x reference clock division rate (when internal PLL selected) = DCLKI input frequency x reference clock division rate (when DCLKI selected) Horizontal frequency = Pixel frequency/Horizontal total pixel count Vertical frequency = Horizontal frequency/Vertical total raster count MB86296S 69 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.5.2 Interlace display CORAL can perform both a non-interlace display and an interlace display. When the DCM register synchronization mode is set to interlace video (11), images in memory are output in odd and even rasters alternately to each field, and one frame (odd + even fields) forms one screen. When the DCM register synchronization mode is set to interlace (10), images in memory are output in raster order. The same image data is output to odd fields and even fields. Consequently, the count of rasters on the screen is half of that of interlace video. However, unlike the non-interlace mode, there is a distinction between odd and even fields depending on the phase relationship between the horizontal and vertical synchronous signals. Odd Eve n Non-Interlace Interlace Video Interlace Fig. 5.4 Display Difference between Synchronization Modes MB86296S 70 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.6 Video Interface, NTSC/PAL Output To achieve NTSC/PAL signals, a NTSC/PAL encoder must be connected externally as shown below: CORAL AOUTR AOUTG AOUTB CSYNC CLK 14.318 MHz NTSC Encoder R-IN G-IN B-IN CSYNC-IN Fsc-IN VIDEO-OUT 1/4 Fig. 5.6 Example of NTSC/PAL Encoder Connection Note) The neither CSYNC and VSYNC pins are impossible to output the 2.5H width signal. MB86296S 71 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.7 Programmable YCbCr/RGB conversion for L1-layer display L1-layer can display video data in YCbCr format but RGB conversion coefficients are hard-wired and fixed about previous products. Coral-PA can program RGB conversion coefficients by registers. YCbCr data is converted by following expression. R = a11*Y + a12*(Cb 128) + a13*(Cr-128) + b1 - G = a21*Y + a22*(Cb 128) + a23*(Cr-128) + b2 - B = a31*Y + a32*(Cb-128) + a33*(Cr-128) + b3 aij ---- 11bit signed real ( lower 8bit is fraction, two's complement ) bi ----- 9bit signed integer ( two's complement ) It is represended by matrix operation. R Y G = A Cb-128 + b B Cr-128 where a11 a12 a13 a21 a22 a23 a31 a32 a33 b1 b2 b3 A= ,b= These parameters are set on registers shown bellow. L1YCR0 (a11,a12), L1YCR1(a13,b1) L1YCG0 (a21,a22), L1YCG1(a23,b2) L1YCB0 (a31,a32), L1YCB1(a33,b3) Same conversion with previous products is applied by initial values of these registers after reset. The register values just after reset is as follow. a11 = 0x12b (299/256) , a12 = 0x0, a13 = 0x198 (408/256) a21 = 0x12b (299/256), a22 = 0x79c (-100/256), a23 = 0x72f (-206/256) a31 = 0x12b (299/256), a32 = 0x204 (516/256), a33 = 0x0 b1= b2= b3= 0x1f0 (-16) Addition of a constant value into b means inclease of brightness. It is possible to control brightness, contrast, hue , color saturation by change these parameters. Multiplication of a constant scalar value greater than one into A means increase of contrast. Two dimentional rotation of Cb-128 and Cr-128 means change of hue. Color saturation is intensity of color, relative to Y-component. New coefficients including these changes can be got by following expression. MB86296S 72 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL A = c1 A0 b = bo + 10 0 0 cos(t) sin(t) 0 -sin(t) cos(t) c3 c3 c3 100 c1 0 0 c2 0 = A0 0 cos(t)c1c2 0 0 c2 0 -sin(t)c1c2 0 sin(t)c1c2 cos(t)c1c2 A0 , b0 : initial value c1: contrast parameter, 1 is standard. 1.2 is stronger, for example. c2: color saturation parameter, 1 is standard. 0 means mono chrome image. c3: brightness parameter, 0 is standard. t : hue rotation parameter, 0-deg is standard Note: new aij and bi should be clipped in valid range of value for corresponding registers. MB86296S 73 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.8 DCLKO shift 1) Delay DCLKO delay function is available if internal PLL is used for DCLK. CKDe-bit of DCM3 enables this function. Delay number is specified at CKDn-field of DCM3 register. CKDn 00000 00001 00010 : 11110 11111 delay t 1.5t 2t : 16t 16.5t t= one cycle of internal PLL or 2.5ns (400MHz osc). 2) Inversion DCLKO inversion is also available with/without delay function. This function is effective with no relation to DCLK clock source. CKinv-bit of DCM3 enables this function. 7.9 Synchronous register update of display To update position related parameters without disturbing display, it is need to update synchronously with VSYNC interrupt and finish at a time. This synchronous register update mode eases this limitation. In this mode, written parameters are hold in intermediate registers and update at once synchronously with VSYNC. RUM bit of DCM3 register enables this mode. RUF-bit of DCM3 register controls start of update and shows whether update is done or not. MB86296S 74 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 7.10 Dual Display This function enables to display for two screens in which including layers can be selected respectively. MSen-bit of MSC register enables this function. SC0en-field of MSC register defines which layers and cursors are included in screen "0". SC1en-field of MSC register defines which layers and cursors are included in screen "1". bit-0 --- L0 is included bit-1 --- L1 is included : bit-5 --- L5 is included bit-6 --- Cursor0 is included bit-7 --- Cursor1 is included A layer or cursor can be included in both screens or one screen. There are two modes to output two screens. In parallel mode, one screen is output at digital output while another screen is output at analog output. In multiplex mode, two screens are multiplexed and output at digital output. (1) parallel output mode DCLKO(SDR) DCLKO(DDR) DE Digital RGB Analog RGB sc0 sc1 sc0 sc1 sc0 sc1 Note: Analog RGB is shown as corresponding data value (2) multiplex output mode DCLKO(SDR) DCLKO(DDR) DE Digital RGB Analog RGB sc0 sc1 sc0 sc1 sc1 sc0 sc1 sc1 sc1 MB86296S Note: Analog RGB is shown as corresponding data value 75 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL In DDR (double data rate) DCLKO mode, two ouput phases can be identified both edge of DCLKO. In SDR (sindle data rate) DCLKO mode, two output phases cab be identified an edge of HSYNC or DE. DCLKO(SDR) HSYNC Digital RGB DE even clocks ref edge sc0 is first sc0 sc1 POM(parallel output mode) bit in DCM3 register definess which output mode is used, parallel or multiplex. CKddr( clock for double data rate) bit in DCM3 registerdefiness which DCLKO clock mode is used, SDR or DDR. The dual display function can not be used with external sync mode. MB86296S 76 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 8. Video Capture 8.1 Video Capture function 8.1.1 Input data Formats The digital video stream of ITU RBT-656 or RGB666 format conformity is inputted (for details refer to 8.5 external video signal input conditions). 8.1.2 Capturing of Video Signal "Coral-PA" becomes effective when VIE of a video capture mode register (VCM) is 1, and it is CCLK. Synchronizing with a clock, video stream data is captured from 8-bit VI pin or 20-bit RGB input pin. 8.1.3 Non-interlace Transformation Captured video graphics can be displayed in non-interlaced format. Two modes (BOB and WEAVE) can be selected at non-interlace transformation. - BOB Mode In odd fields, the even-field raster generated by average interpolation are added to produce one frame. In even fields, the odd-field raster generated by average interpolation are added to produce one frame. In order to choose BOB mode, while enable vertical interpolation in VI bit of a VCM (Video Capture Mode) register, the L1IM bit of L1M (L1-layer Mode) register is set as 0. - WEAVE Mode Odd and even fields are merged in the video capture buffer to produce one frame. Vertical resolutions in the WEAVE mode are higher than those in the BOB mode but raster dislocation appears at moving places. In order to choose WEAVE mode, while disable vertical interpolation in VI bit of a VCM (Video Capture Mode) register, the L1IM bit of L1M (L1-layer Mode) register is set as 1. MB86296S 77 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 8.2 Video Buffer 8.2.1 Data Form The video capture unit of MB86296 "Coral-PA" accepts YUV422 video data primarily, but RGB video data is also accepted via an internal RGB preprocessor which converts RGB to YUV422. Captured pixels are stored in YCbCr format in graphics memory, 16 bits per pixel. The video data is converted to RGB when it is displayed. 31 Y1 24 23 Cr 16 15 Y0 87 Cb 0 Y0,Y1 Cr,Cb Y7 7 Y6 6 Y5 5 Y4 4 Y3 3 Y2 2 Y1 1 Y0 0 C7 C6 C5 C4 C3 C2 C1 C0 8.2.2 Synchronous Control Writing to the graphics memory of video image data and scan for a display are performed independently. The graphics memory for video captures is controlled by the ring buffer system. It displays the frame, when the image data for one frame can be preparing on a memory. When the frame rate of a video capture differs from the frame rate of a display, the continuation display of top omission or the same frame occurs. 8.2.3 Area Allocation Allocate an area of about 2.2 frames to the video capture buffer. The size of this area is equivalent to the size that considers the margin equivalent to the double buffer of the frame. Set the starting address and upper-limit address of the area in the CBOA/CBLA registers. Here, specify the raster start position as the upper-limit address. To allocate n rasters as the video capture buffer, set the upper-limit value as follows: CBLA = CBOA + 64 (n-2) x CBW In addition, the head addresses of n+1 raster are 64nxCBW, and CBLA+2 raster becomes a buffer domain. For reduced display, allocate the buffer area of the reduced frame size. MB86296S 78 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 8.2.4 Window Display The captured video picture is displayed using L1 layer. The whole or a part captured picture can be displayed as the whole screen or a window. When performing a capture display, L1 layer is set as capture synchronous mode (L1CS=1). In this mode, L1 layer display displays the newest frame in a video capture buffer. Usually, the display address used in the mode is disregarded. The stride of L1 layer needs to be in agreement with the stride of a video capture buffer. When not in agreement, the picture distorted aslant is displayed. The display size of L1 layer is made in agreement with the picture size after reduction of a video capture. Invalid data will be displayed if the display size of L1 layer is set up more greatly than capture picture size. Although selection of a RGB display and a YCbCr display can be performed in L1 layer, in performing a video capture, it chooses YcbCr form (L1YC=1). 8.2.5 Interlace Display It is possible to display the picture taken in to the video capture buffer in WEAVE mode in an interlace. A setup confirms WEAVE mode and chooses an interlace & video display with display scan. However, when display scan is asynchronous, flicker will come out in a scene with a motion. In order to prevent this, OO (Odd Only) bit of a CBM (Capture Buffer Mode) register is set as 1. When synchronizing display scan with a capture, a capture input and a display output can be made to correspond to 1 to 1. In this case, the difference of flicker of an input and an output is lost. Please refer to "8.8 Capture synchronous display." MB86296S 79 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 8.3 Scaling 8.3.1 Down-scaling Function When the CM bits of the video capture mode register (VCM) are 11, Coral reduces the video screen size. The reduction can be set independently in the vertical and horizontal scales. The reduction is set per line in the vertical direction and in 2-pixel units in the horizontal direction. The scale setting value is defined by an input/output value. It is a 16-bit fixed fraction where the integer is represented by 5 bits and the fraction is represented by 11 bits. Valid setting values are from 0800H to FFFFH. Set the vertical direction at bit 31 to bit 16 of the capture scale register (CSC) and the horizontal direction at bits 15 to bit 00. The initial value for this register is 08000800H (once). An example of the expressions for setting a reduction in the vertical and horizontal directions is shown below. Reduction in vertical direction Reduction in horizontal direction 576 -> 490 lines 1.176x2048=2408 720 -> 648 pixels 1.111x2048=2275 576/490 = 1.176 -> 0968H 720/648 = 1.111 -> 08E3H Therefore, 096808E3H is set in CSC. The capture horizontal pixel register (CHP) is used to limit the number of pixels processed during scaling. It is not used to set scaling values. Clamp processing is performed on the video streaming data outside the values set in CHP. Usually, the defaults for these registers are used. 8.3.2 Up-scaling Function Coral is able to enlarge the size of a video capture picture by the factor of 2 in both the horizontal and vertical directions. This feature can be used to realize full-screen modes of video input streams which have a resolution less than actual display size. In order to use magnify (up-scaling) mode, the horizontal and vertical factor must be less than one. Do initialize the following registers as follows : Set the magnify flag in the L1-layer mode register of the display controller. Set the picture source size (before magnification) into CMSHP and CMSVL. Set the final picture size (after magnification) into CMDHP and CMDVL. An example of the expressions for setting an enlargement in the vertical and horizontal directions is shown below : If the input picture size is 480x360 and the display picture size is 640x480, then the parameters for each register are as follows. HSCALE=(480/640)*2048=0x0600 VSCALE=(360/480)*2048=0x0600 CMSHP=0x00f0 CMSVL=0x0168 CMDHP=0x0140 CMDVL=0x01e0 L1WW=0x0280 L1WH=0x01df MB86296S 80 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Note: - Smooth continuation operation to Down Scaling mode and Up Scaling mode cannot be performed. The picture disorder of some arises at the time of a change. This is the restrictions for Up Scaling mode and Down Scaling mode using the same interpolate circuit. MB86296S 81 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 8.3.2 Flow of image processing As for the capture image displayed on L1 layer window, image processing is performed by the following flow. VideoInput (656/RGB) Color conversion YUV422 YUV / RGB Non-interlace interpolation RGB matrix MB86296 656(YUV422) On / Off Capture buffer controller horizontal LPF horizontal down scaling horizontal interpolator horizontal up scaling vertical LPF Line Buffer vertical down scaling vertical interpolator vertical up scaling Scaler Display Controller Figure 8.1 Flow of image processing * Non-interlace interpolation processing When VI of a video capture mode register (VCM) is 0, an interlace screen is interpolated vertically using the data in the same field. A screen is doubled vertically. When VI is 1, it is not interpolated vertically. * Horizontal low-pass filter processing As a preprocessing when scaling down a picture horizontally, a low-pass filter can be covered horizontally. Regardless of scaling up and scaling down of a picture, ON/OFF is possible for a level low path filter (LPF). The horizontal low-pass filter consists of FIR filters of five taps. A coefficient is specified in the following register. CHLPF_Y CHLPF_C Horizontal LPF Luminance element and RGB element coefficient code Horizontal LPF chrominance element coefficient code MB86296S 82 VRAM Video Output FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL The coefficient is specified by the coefficient code in two bits independently by luminance (Y) signal and chrominance (Cb and Cr) signals. The coefficient is a symmetric coefficient. CHLPF_x 00 01 10 11 K0 0 0 0 3/32 K1 0 1/4 3/16 8/32 K2 1 2/4 10/16 10/32 K3 0 1/4 3/16 10/32 K4 0 0 0 3/32 Horizontal LPF becomes turning off (through) because of the setting of the coefficient code "00". Note: - In the case of Native RGB mode (NRGB=1), only a setup of CHLPF_Y code becomes effective. * Down and Up scaling processing of horizontal direction Please set bit15-00 of capture scale register (CSC) to do the down and up scaling processing of horizontal direction. Horizontal direction is scaled down before writing in VRAM. Horizontal direction is scaled up after reading from VRAM. The interpolation filter processing of luminance (Y) signal is done by cubic interpolation (Cubic Interpolate) method. The interpolation filter processing of chrominance (Cb and Cr) signal is done by BiLinear interpolation (BiLinear Interpolate) method. The interpolation filter processing of Native-RGB signal is done by cubic interpolation (Cubic Interpolate) method. * Vertical low-pass filter processing The low-pass filter can be put on the vertical direction as a preprocessing when the image is scaled down to the vertical direction. Vertical low-pass filter (LPF) can be set to turning on regardless of the scaling up or down of the vertical direction. A vertical low-pass filter is composed of the FIR filter of three taps. The coefficient is specified by the following register. CVLPF_Y CVLPF_C Vertical LPF Luminance element and RGB element coefficient code Vertical LPF chrominance element coefficient code The coefficient is specified by the coefficient code in two bits independently by luminance (Y) signal and chrominance (Cb and Cr) signals. The coefficient is a symmetric coefficient. MB86296S 83 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL CVLPF_x 00 01 10 11 K0 0 1/4 3/16 Prohibition of setting K1 1 2/4 10/16 K2 0 1/4 3/16 Vertical LPF becomes turning off (through) because of the setting of the coefficient code "00". Note: - In the case of Native RGB mode (NRGB=1), only a setup of CVLPF_Y code becomes effective. * Down and up scaling processing of Vertical direction Please set bit31-16 of capture scale register (CSC) to do the down and up scaling processing in the vertical direction. The vertical direction is scaled down before writing in VRAM. The vertical direction isscaled up after reading from VRAM. The interpolation filter processing of luminance (Y) signal is done by cubic interpolation (Cubic Interpolate) method. The interpolation filter processing of chrominance (Cb and Cr) signal is done by BiLinear interpolation (BiLinear Interpolate) method. The interpolation filter processing of Native-RGB signal is done by cubic interpolation (Cubic Interpolate) method. MB86296S 84 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 8.4 Error handling 8.4.1 Error detect function In the input video data, when expected control code and synchronized signal cannot be detected, it becomes an error. When the error occurs, interrupt is generated in Bit16 of host CPU interface register IST and status is returned to each register of the video capture. MB86296S 85 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 8.5 External video signal input conditions 8.5.1 RTB656 YUV422 input format The ITU R.BT-656 format is widely used for digital transmission of NTSC and PAL signals. The format corresponds to YUV422. Interlaced video display signals can be captured and displayed non-interlaced with linear interpolation. When the VIE bit of the video capture mode register (VCM) is 1, Coral is able to capture video stream data from the 8-bit VI pin in synchronization with the CCLK clock. In this mode, only a digital video stream conforming to ITU-RBT656 can be processed. For this reason, a Y,Cb,Cr 4:2:2 format to which timing reference codes are added is used. The video stream is captured according to the timing reference codes; Coral automatically supports both NTSC and PAL. However, to detect error codes, set NTSC/PAL in the VS bit of VCM. If NTSC is not set, reference the number of data in the capture data count register (CDCN). If PAL is not set, reference the number of data in the capture data counter register (CDCP). If the reference data does not match the stream data, bit 4 to bit 0 of the video capture status register (VCS) will be values other than 0000. 1) RTB656 input format VI[7:0] Synchronous code and image data (Cb,Y,Cr,Y) are input as data of eight multiple bits synchronizing with 27MHz clock, and an valid pixel is transmitted while placed between a 4T 4T Blanking data 80,10,80,10,80,. H-BLANK 276T 288T SAV Multiplexed video data Cb,Y,Cr,Y,Cb,Y,Cr,Y,..... EAV VI[7:0] 8 bit EAV ACTIVE-VIDEO 1440T [1440T] ACTIVE-VIDEO -LINE 1716T 1728T synchronous code named SAV and EAV. SAV : Beginning code of active video data (4 Byte) EAV : End code of active video data (4 Byte) T : 27MHz [ ] : 625/50 series (PAL) BLANKING TIMING TIMING BLANKING 720 PIXELS YUV4:2:2 DATA PERIOD REF-CODE REF-CODE PERIOD ... 80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 ... Cr718 Y719 FF 00 00 EAV 80 10 ... MB86296S 86 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 2) RTB656 synchronous code (4 Byte) format Word SYNC code (static) first second 0 0 0 0 0 0 0 0 third 0 0 0 0 0 0 0 0 1 (static) F 0:first field H 0:SAV 1:EAV P3 Guard bit P2 Guard bit P1 Guard bit P0 Guard bit 1 1 1 1 1 1 1 1 EAV/SAV forth 1:second field Bit 7 6 5 4 3 2 1 0 V 0:ACTIVE-VIDEO 1:VBI 3) SAV/EAV timing base signal Bit 80 9D AB B6 C7 DA EC F1 7 1 1 1 1 1 1 1 1 6 F 0 0 0 0 1 1 1 1 5 V 0 0 1 1 0 0 1 1 4 H 0 1 0 1 0 1 0 1 3 P3 0 1 1 0 0 1 1 0 2 P2 0 1 0 1 1 0 1 0 1 P1 0 0 1 1 1 1 0 0 0 P0 0 1 1 0 1 0 0 1 Function static MB86296S 80 : SAV code of first field valid pixel period (Active-video) 9D : EAV code of first field valid pixel period (Activev ideo) AB : SAV code of first field vertical retrace line period B6 : EAV code of first field vertical retrace line period C7 : SAV code of second field valid pixel period (Active-video) DA : EAV code of second field valid pixel period (Active-video) EC : SAV code of second field vertical retrace line period F1 : EAV code of second field vertical retrace line period 87 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 8.5.2 RGB input format There are the two data-processing methods in RGB input video capture function. One is the method of processing with Native RGB. Another is the method of converting RGB into YUV422 by the internal RGB pre processor. RGB input function is suitable for relatively high speed non-interlaced video signals but the deinterlacing operation is not available in this mode. The maximum input rate is 66Mpixel/sec. RGB component data is 6bit. Note: - In Native RGB mode, NRGB=1 is set up. 1) RGB Input Signals The signals used for RGB video capture are not assigned dedicated terminals but share same pins with other functions. Name RGBCLK RI5-0 GI5-0 BI5-0 VSYNCI HSYNCI Note : - input pins are shared with the ITU656 input and memory data bus. - the VIS bit of the VCM (video capture mode) register selects which mode (ITU656 or RGB) is used. I/O Function Input Clock for RGB input Input Red component value Input Green component value Input Blue component value Input Vertical sync for RGB capture Input Horizontal sync for RGB capture 2) Captured Range Instead of embedded sync code method used in ITU656 mode, the capture range in RGB mode is specified by the following register parameters: a) RGB input mode of capture: Set RGB666 input flag(VIS) in VCM. In Native RGB mode, NRGB in VCM =1 is set up. b) HSYNC Cycle: Set the number of HSYNC Cycles in RGBHC. c) Horizontal Enable area: Set enables area start position and enable picture size into RGBHST and RGBHEN. d) Vertical Enable area: Set enables area start position and enable picture size into RGBVST and RGBVEN. MB86296S FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL The Captured area is defined according to the following parameters. Each parameter is set independently at the respective register.: RGBHC RGBHST RGBHEN(~840) VSYNC RGBVST RGBHC RGBHST RGBHEN RGBVST RGBVEN RGB input Hsync Cycle RGB input Horizontal enable area STart position RGB input Horizontal enable area size RGB input Vertical ENable area STart position RGB input Vertical ENable area size Note: The actual parameter settings are little different from the above. The details, please refer "Explanation of Registers". e) Convert Matrix Coefficient In order to change the color conversion matrix, set up RGBCMY, RGBCb, RGBCr and RGBCMb. Note: - The maximum horizontal enable area size(RGBHEN) which can be captured is 840 pixels. This is the restriction by line buffer size in a video capture module. MB86296S HSYNC RGBVEN (~4096) captured 89 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 3) Input Operation At the time of a RGB input, the synchronization of data is taken by VSYNC and SYNCI, which are inputted with Data RI, GI and BI. Input rule of HSYNCI The positive or negative edge of VINHSYNC is considered as a horizontal synchronization by register setup(HP). Input the signal of 1 or more RGBCLKs-(8 40+ )RGBCLK cycle. RGBCLK HSYNCI HSYNC(internal RGB input function) More than 1 RGBCLK e e e e e ~840RGBCLK+ (HBLANK) e Note: - The maximum horizontal enable area size(RGBHEN) which can be captured is 840 pixels. This is the restriction by line buffer size in a video capture module. Valid data input rule to HSYNC The valid image data input rule to HSYNC is shown. Input data is inputted synchronizing with HSYNC of each line. (The synchronization of data needs to make a synchronization establish by HSYNC in each line unit. Since the sampling clock of image data is generated from HSYNC, it is because a clock may have jitter per line.) RGBCLK HSYNCI RGBHST RI5-0 GI5-0 BI5-0 captured MB86296S 90 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Input rule of VINVSYNC A VSYNCI signal is synchronizing with HSYNCI. Moreover, VSYNCI is sampled by HSYNCI , and it considers as a VSYNC signal. Width is made into at least one line or more although a VSYNCI signal does not need to synchronize with HSYNC at this time. The positive or negative of VSYNCI is set to VSYNC by register setup(VP). ~840RGBCLK+ RGBCLK HSYNC(internal RGB input function) 1RGBCLK More than 1 line VSYNCI valid line input rule to HSYNC The valid image data input rule to VSYNC is shown. HSYNCI VSYNCI RGBVST start to capture MB86296S 91 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 4) Conversion Operation RGB input data is converted to YCbCr by the following matrix operation : Y= Cb= Cr= a11*R + a12*G + a13*B + b1 a21*R + a22*G + a23*B + b2 a31*R + a32*G + a33*B + b3 aij : bi: 10bit signed real ( lower 8bit is fraction ) 8bit unsigned integer Note: - registers can define each coefficient. - C and Cr components are reduced to half after this operation to form in 4:2:2 format. b MB86296S 92 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 5) RGB555 Mode As an alternative method, a special RGB555-mode can be used which is dedicated for applications where grabbed pictures should be processed further. In this mode, a single buffer is used instead of a ring buffer. In addition, data is directly stored in Coral's RGB555 format in the L1-Layer (see settings of the CBM register). This makes it possible to copy rectangular areas from the L1-layer directly to the texture buffer or to other memory locations using the BitBlt function. Note that the input and output frame rate should be identical if a single buffer method is used and that the lower bits are ignored to form the RGB555 format. MB86296S 93 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 9. GEOMETRY ENGINE 9.1 Geometry Pipeline 9.1.1 Processing flow The flow of geometry is shown below. Object coordinates (OC) MVP Transformation Clip coordinates (CC) Clipping Back face culling 3D-2D Transformation Normalized device coordinates (NDC) View port transformation Drawing (device) coordinates (DC) MB86296S 94 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 9.1.2 Model-view-projection (MVP) transformation (OCCC coordinate transformation) The geometry engine transforms the vertex of the "OC" coordinate system specified by the G_Vertex packet to the "CC" coordinate system according to the coordinate transformation matrix (OC CC Matrix) specified by the G_LoadMatrix packet. The "OC CC Matrix" is a "4 x 4" matrix consisting of a ModelView matrix and a Projection matrix. If "Zoc" is not contained in the input parameter of the G_Vertex packet (Z-bit of GMDR0 is off), (OC CC) coordinate transformation is processed as "Zoc = 0". When GMDR0[0] is 0 (orthogonal projection transformation), OC CC coordinate transformation is processed as "Wcc = 1.0". OC: Object Coordinates CC: Clip Coordinates Xcc Ycc Zcc Wcc = Ma0 Ma1 Ma2 Ma3 Mb0 Mb1 Mb2 Mb3 Mc0 Mc1 Mc2 Mc3 Md0 Md1 Md2 Md3 Xoc Yoc Zoc 1 Ma0 to Md3: OC CC Matrix Xoc to Zoc: X, Y, and Z of OC coordinate system Xcc to Woc: X, Y, Z, and W of CC coordinate system 9.1.3 3D-2D transformation (CCNDC coordinate transformation) The geometry engine divides "XYZ" of the "CC" coordinate system by "Wcc" (Perspective Division). NDC: Normalized Device Coordinates Xndc Yndc Zndc = Xcc 1/Wcc Ycc Zcc Xndc to Zndc: X, Y, and Z of "NDC" coordinate system MB86296S 95 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 9.1.4 View port transformation (NDCDC coordinate transformation) The geometry engine transforms "XYZ" of the "NDC" coordinate system to the "DC" coordinate system according to the transformation coefficient specified by G_ViewPort and G_DepthRange. "X_Scaling,X_Offset" and "Y_Scaling,Y_Offset" are coefficients to be mapped finally to Frame Buffer. Xdc and Ydc must be included within the drawing input range (-4096 to 4095). "Z_Scaling" and "Z_Offset" are coefficients to be mapped finally to "Z Buffer". "Zdc" must be included within the "Z Buffer" range (0 to 65535). DC: Device Coordinates Xdc = X_Scaling*Xndc + X_Offset Ydc = Y_Scaling*Yndc + Y_Offset Zdc = Z_Scaling*Zndc + Z_Offset 9.1.5 View volume clipping Expression for determination The expression for determining the CORAL view volume clipping is shown below. W clipping is intended to prevent the overflow caused by 1/W. Xmin*Wcc Xcc Xmax*Wcc Ymin*Wcc Ycc Ymax*Wcc Zmin*Wcc Zcc Zmax*Wcc Wmin Wcc Note: Xmin, Xmax, Ymin, Ymax, Zmin, Zmax, and Wmin are the clip boundary values set by the G_ViewVolumeXYClip/ZClip/WClip packet. Clipping-on/-off View volume clipping-on/-off can be switched by using the clip boundary values set by the G_ViewVolumeXYClip/Zclip/WClip packet. To switch view volume clipping to off, set the maximum and minimum values of the geometry data format (IEEE single-precision floating point(*1)) in the "Clip.max" value(*2) and "Clip.min" value(*3), respectively. In this case, `All coordinate transformation results' can be evaluated as within view volume range, making it possible to obtain the effect of view volume clipping-off. This method is valid only when W clipping does not occur. When a clip boundary value (Wmin) that causes W clipping to occur is set, clipping is also performed for each clip area. Consequently, set an appropriate clip boundary value for Clip. Max value. and Clip. Min value., respectively. If other values are set in "Clip.max" and Clip.min, view volume clipping-on operates. The coordinate transformation result is always compared with the values set in "Clip.max" and "Clip.min". *1: Maximum value = 0x7f7fffff, minimum value = 0xff7fffff *2: Xmin,Ymin, Zmin, Wmin *3: Xmax, Ymax, Zmax MB86296S 96 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL An example of the G_ViewVolumeZclip packet is shown below. 0xf1012010 //Setting of GMDR0 0x00000000 //Data format: Floating point data format 0x45000000 //G_ViewVolumeZclip packet 0xff7fffff //Zmin.float setting value (minimum value of IEEE single-precision floating point) 0x7f7fffff //Zmax.float setting value (maximum value of IEEE single-precision floating point) Example of G_ViewVolumeZclip Packet when Z Clipping Off "W" clipping at orthogonal projection transformation Relationship with drawing clip frame "W" at orthogonal projection transformation (GMDR0[0] = 0) is treated as "Wcc=1.0". For this reason, to suppress "W" clipping, the set "Wmin" value must be larger than 0 and 1.0 or less. For the following reasons, the clip boundary values of the view volume should be set so that the values after DC coordinate transformation will be larger than the drawing clip frame (2 pixels or more). (1) "XY" on the view volume clip frame of the "CC" coordinate system may be drawn one pixel outside or inside the frame due to an operation error when it is finally mapped to the "DC" coordinate system. (2) When the end point of a line overlaps the view volume frame mapped to the "DC" coordinate system, there are two cases, where the dots on the frame are drawn, and not drawn depending on the specifying of the line drawing attribute (end point drawing/non-drawing). (3) When the start point of a line overlaps the view volume frame mapped to the "DC" coordinate system, the dots on the frame are always drawn. When the line drawing attribute is `end point non-drawing,' the dots on the frame are drawn at the starting point, but they may not be drawn at the end point. (4) When applying to triangle and polygon drawing the rasterizing rule `dots containing center of pixel drawn. Dots on right side and base of triangle not drawn.' depending on the value of the fraction, a gap may be produced between the right side and base of the frame. Drawing area "DC" Coordinates image of view volume clip frame Drawing clip frame A space of two pixels or more is required. MB86296S 97 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 9.1.6 Back face culling In CORAL, a triangle direction can be defined and a mode in which drawing for the back face is inhibited (back face culling) is supported. The on/off operation is controlled by the GMDR2[0] setting. GMDR2[0] must be set to 1 only when back face carling is required. When back face culling is not required such as in `line,' `point,' and `polygon primitive,' GMDR2[0] must be set to 0. MB86296S 98 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 9.2 Data Format 9.2.1 Data format The supported data formats are 32-bit single-precision floating-point format, 32-bit fixed-point format, integer packed format, and RGB packed format. All internal processing is performed in the floatingpoint format. For this reason, the integer packed format, fixed-point format, and RGB packed format must be converted to the floating-point format. The processing speeds in these formats are slightly lower than in the 32-bit single-precision floating-point format. The data format to use is selected by setting the GMDR0 register. (1) 32-bit single-precision floating-point format 31 30 s 23 22 0 s: Sign bit (1 bit) e: Exponent part (8 bits) f: Mantissa (23 bits): `1.f' shows the fraction. `1' is a hidden bit. The numerical value of the floating-point format becomes (-1)s(1.f)2(e-127) (0 < e < 255). (2) Signed fixed-point format (SFIX16.16) 31 30 s e f 16 15 Frac 0 s: Sign bit (1 bit) int: Integer (15 bits) frac: Fraction (16 bits) 31 30 s Int (3) Signed integer packed format (SINT16.SINT16) s: Sign bit (1 bit) int: Integer (15 bits) (4) RGB packed format 31 reserved Y.int 16 15 14 s X.int 0 24 23 R 16 15 G 87 B 0 R, G, B: Color bits (8 bits) (5) ARGB packed format 31 A 24 23 R 16 15 G 87 B 0 A: Alpha bits (8 bits) R, G, B: Color bits (8 bits) MB86296S 99 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 9.3 Setup Engine 9.3.1 Stup processing e The vertex data transformed by the geometry engine is transferred to the setup engine. CORAL has a drawing interface that is compatible with the MB86290A. It operates parameters for various slope calculations, etc., with the setup engine. When the obtained parameters are set in the drawing engine, the final drawing processing starts. 9.4 Log Output of Device Coordinates A function is provided to output device coordinates (DC) data obtained by view port conversion to local memory (graphics memory). 9.4.1 Log output mode Drawing & log output command Log output of drawing coordinates (device coordinates) can be performed concurrently with nclip_Points.int primitive drawing. Log output can be controlled using the command with log output on/off attribute; log output is performed only when the log output on attribute is specified. Log output dedicated command When the log output dedicated command is used, log output of the device coordinates can be performed. 9.4.2 Log output destination address The log output destination address is controlled by the device coordinates log pointer. Once set an address, this pointer automatically increment an output address. MB86296S 100 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10. DRAWING PROCESSING 10.1 Coordinate System 10.1.1 Drawing coordinates After the calculation of coordinates by the geometry engine, CORAL draws data in the drawing frame in the graphics memory that finally uses the drawing coordinates (device coordinates). Drawing frame is treated as 2D coordinates with the origin at the top left as shown in the figure below. The maximum coordinates is 4096 x 4096. Each drawing frame is located in the Graphics Memory by setting the address of the origin and resolution of X direction (size). Although the size of Y direction does not need to be set, Y coordinates which are max. at drawing must not be overlapped with other area. In addition, at drawing, specifying the clip frame (top left and bottom right coordinates) can prevent the drawing of images outside the clip frame. X (max. 4096) Origin Drawing frame size X Drawing frame size Y (Xmin, Ymin) Clip frame Y (max. 4096) (Xmax, Ymax) MB86296S 101 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.1.2 Texture coordinates Texture coordinate is a 2D coordinate system represented as S and T (S: horizontal, T: vertical). Any integer in a range of -8192 to +8191 can be used as the S and T coordinates. The texture coordinates is correlated to the 2D coordinates of a vertex. One texture pattern can be applied to up to 4096 x 4096 pixels. The pattern size is set in the register. When the S and T coordinates exceed the maximum pattern size, the repeat, cramp or border color option is selected. S (max. 8192) T (max. 8192) max. 4096 pixels max. 4096 pixels Origin Texture pattern 10.1.3 Frame buffer For drawing, the following area must be assigned to the Graphics Memory. The frame size (count of pixels on X direction) is common for these areas. Drawing frame Z buffer The results of drawing are stored in the graphical image data area. Both the direct and indirect color mode are applicable. Z buffer is required for eliminating hidden surfaces. In 16 bits mode, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. This area is used for polygon drawing. 1 bit is required per 1 pixel. Polygon drawing flag buffer MB86296S 102 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.2 Figure Drawing 10.2.1 Drawing primitives CORAL has a drawing interface that is compatible with the MB86290A graphics controller which does not perform geometry processing. The following types of figure drawing primitives are compatible with the MB86290A. * * * * * * Point Line Triangle High-speed 2DLine High-speed 2DTriangle Polygon 10.2.2 Polygon drawing function An irregular polygon (including concave shape) is drawn by hardware in the following manner: 1. Execute PolygonBegin command. Initialize polygon drawing hardware. 2. Draw vertices. Draw outline of polygon and plot all vertices to polygon draw flag buffer using high-speed 2DTriangle primitive. 3. Execute PolygonEnd command. Copy shape in polygon draw flag buffer to drawing frame and fill shape with color or specified tiling pattern. MB86296S 103 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.2.3 Drawing parameters The MB86290A-compatible interface uses the following parameters for drawing: The triangles (Right triangle and Left triangle) are distinguished according to the locations of three vertices as follows (not used for high-speed 2DTriangle): V0 Long edge Upper edge Upper triangle Upper edge Upper triangle V0 Long edge V1 V2 Lower edge Lower triangle Right-hand triangle V1 Lower edge Lower triangle Left-hand triangle V2 The following parameters are required for drawing triangles (for high-speed 2DTriangle, X and Y coordinates of each vertex are specified). Ys Xs,Zs,Rs,Gs,Bs,Ss,Ts,Qs XUs Upper edge start Y coordinates dXdy dZdy dRdy dGdy dBdy dSdy dTdy dQdy dXUdy dZdx,dRdx,dGdx,dBdx, dSdx,dTdx,dQdx XLs dXLdy USN Lower edge start Y coordinates LSN Note: Be careful about the positional relationship between coordinates Xs, XUs, and XLs. For example, in the above diagram, when a right-hand triangle is drawn using the parameter that shows the coordinates positional relationship Xs (upper edge start Y coordinates) > XUs or Xs (lower edge start Y coordinates) > XLs, the appropriate picture may not be drawn. MB86296S 104 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Ys Xs XUs XLs Zs Rs Gs Bs Ss Ts Qs dXdy dXUdy dXLdy dZdy dRdy dGdy dBdy dSdy dTdy dQdy USN LSN dZdx dRdx dGdx dBdx dSdx dTdx dQdx Y coordinates start position of long edge in drawing triangle X coordinates start position of long edge corresponding to Ys X coordinates start position of upper edge X coordinates start position of lower edge Z coordinates start position of long edge corresponding to Ys R color value of long edge corresponding to Ys G color value of long edge corresponding to Ys B color value of long edge corresponding to Ys S coordinate of textures of long edge corresponding to Ys T coordinate of textures of long edge corresponding to Ys Q perspective correction value of texture of long edge corresponding to Ys X DDA value of long edge direction X DDA value of upper edge direction X DDA value of lower edge direction Z DDA value of long edge direction R DDA value of long edge direction G DDA value of long edge direction B DDA value of long edge direction S DDA value of long edge direction T DDA value of long edge direction Q DDA value of long edge direction Count of spans of upper triangle Count of spans of lower triangle Z DDA value of horizontal direction R DDA value of horizontal direction G DDA value of horizontal direction B DDA value of horizontal direction S DDA value of horizontal direction T DDA value of horizontal direction Q DDA value of horizontal direction 10.2.4 Anti-aliasing function CORAL performs anti-aliasing to make jaggies less noticeable and smooth on line edges. To use this function at the edges of primitives, redraw the primitive edges with anti-alias lines. ( The edge of line is blended with a frame buffer color at that time. Ideally please draw sequentially from father object.) MB86296S 105 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.3 Bit Map Processing 10.3.1 BLT A rectangular shape in pixel units can be transferred. There are following types of transfer: 1. Transfer from host CPU to Drawing frame memory 2. Transfer between Graphics Memories including Drawing frame Concerning 1 and 2 above, 2-term logic operation is performed between source and destination data and its result can be stored. Setting a transparent color enables a drawing of a specific pixel with transmission. If part of the source and destination of the BLT field are physically overlapped in the display frame, the start address (from which vertex the BLT field to be transferred) must be set correctly. 10.3.2 Pattern data format CORAL can handle three bit map data formats: indirect color mode (8 bits/pixel), direct color mode (16 bits/pixel, 24 bits/pixel), and binary bit map (1 bit/pixel). The binary bit map is used for character/font patterns, where foreground color is used for bitmap = 1 pixel, and background color (background color can be set to be transparent by setting) is applied for bitmap = 0 pixels. MB86296S 106 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.4 Texture Mapping 10.4.1 Texture size CORAL reads texel corresponding to the specified texture coordinates (S, T), and draws that data at the correlated pixel position of the polygon. For the S and T coordinates, the selectable texture data size is any value in the range from 4 to 4096 pixels represented as an exponent of 2. 10.4.2 Texture color Drawing of 8-/16-bit direct color is supported for the texture pattern. For drawing 8-bit direct color, only point sampling can be specified for texture interpolation; only de-curl can be specified for the blend mode. MB86296S 107 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.4.3 Texture Wrapping If a negative or larger than the specified texture pattern size is specified as the texture coordinates (S, T), according to the setting, one of these options (repeat, cramp or border) is selected for the `out-ofrange' texture mapping. The mapping image for each case is shown below: Repeat Cramp Border Repeat This just simply masks the upper bits of the applied (S, T) coordinates. When the texture pattern size is 64 x 64 pixels, the lower 6 bits of the integer part of (S, T) coordinates are used for S and T coordinates. When the applied (S, T) coordinates is either negative or larger than the specified texture pattern size, cramp the (S, T) coordinate as follows instead of texture: S<0 S > Texture X size - 1 S=0 S = Texture X size - 1 Cramp Border When the applied (S, T) coordinate is either negative or larger than the specified texture pattern size, the outside of the specified texture pattern is rendered in the `border' color. MB86296S 108 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.4.4 Filtering CORAL supports two texture filtering modes: point filtering, and bi-linear filtering. Point filtering This mode uses the texture pixel specified by the (S, T) coordinates as they are for drawing. The nearest pixel in the texture pattern is chosen according to the calculated (S, T) coordinates. 0.0 0.5 1.0 1.5 2.0 0.5 1.0 1.5 2.0 Bi- linear filtering The four nearest pixels specified with (S, T) coordinate are blended according to the distance from specified point and used in drawing. 0.0 0.5 1.0 1.5 2.0 C01 C11 0.5 1.0 1.5 2.0 C00 C10 10.4.5 Perspective correction This function corrects the distortion of the 3D perspective in the texture mapping. For this correction, the `Q' component of the texture coordinates (Q = 1/W) is set based on the W component of 3D coordinates of the vertex. When the texture coordinates are large values, the texture may not be drawn correctly when perspective correction is performed. This phenomenon occurs due to the precision limitation of the arithmetical unit for perspective correction. The coordinates for the texture that cannot be drawn normally vary with the value of the Q component; as a guide, when this value is smaller than -2048 or larger than 2048, normal drawing results are less likely to be obtained. MB86296S 109 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.4.6 Texture blending CORAL supports the following three blend modes for texture mapping: Decal This mode displays the selected texture pixel color regardless of the polygon color. Modulate This mode multiplies the native polygon color (CP) and selected texture pixel color (CT) and the result is used for drawing. Rendering color is calculated as follows (CO): C0 = C T x CP This mode selects the display color from the texture color with MSB as a flag. MSB = 1: Texture color MSB = 0: Polygon color Stencil 10.4.7 Bi-linear high-speed mode Bi-linear filtering is performed at high speed by creating normal texture data in advance with four-pixel redundancy for one pixel. One pixel requires information of about four pixels, so an area of four times the normal area is used. This data format can only be used only for the bi-linear filtering mode; it cannot be used for the point sampling mode. The wrapping mode is limited to REPEAT and the color mode islimited to 16 -bit color. MB86296S 110 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 0 1 2 3 4 5 6 7 0 00 01 02 03 04 05 06 07 1 08 09 10 11 12 13 14 15 2 16 17 18 19 20 21 22 23 3 24 25 26 27 28 29 30 31 4 32 33 34 35 36 37 38 39 5 40 41 42 43 44 45 46 47 6 48 49 50 51 52 53 54 55 7 56 57 58 59 60 61 62 63 Normal texture layout (8 x 8 pixels) 0 1 6 7 0 00 01 08 09 01 02 09 10 to 06 07 14 15 07 00 15 08 1 08 09 16 17 09 10 17 18 to 14 15 12 13 15 08 23 16 2 16 17 24 25 17 18 25 26 to 22 23 30 31 23 16 31 24 3 24 25 32 33 25 26 33 34 to 30 31 38 39 31 24 39 32 4 32 33 40 41 33 34 41 42 to 38 39 46 47 39 32 47 40 5 40 41 48 49 41 42 49 50 to 46 47 54 55 47 40 55 48 6 48 49 56 57 49 50 57 58 to 54 55 62 63 55 48 63 56 7 56 57 00 01 57 58 01 02 to 62 63 06 07 63 56 07 00 Texture layout in bi-linear mode (8 x 8 pixels) MB86296S 111 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.5 Rendering 10.5.1 Tiling Tiling reads the pixel color from the correlated tiling pattern and maps it onto the polygon. The tiling determines the pixel on the pattern read by pixel coordinates to be drawn, irrespective of position and size of primitive. Since the tiling pattern is stored in the texture memory, this function and texture mapping cannot be used at the same time. Also, the tiling pattern size is limited to within 64 x 64 pixels. (at 16-bit color) Example of Tiling 10.5.2 Alpha blending Alpha blending blends the drawn in frame buffer to-be-drawn pixel or pixel already according to the alpha value set in the alpha register. This function cannot be used simultaneously with logic operation drawing. It can be used only when the direct color mode (16 bits/pixel) is used. The blended color C is calculated as shown below when the color of the pixel to be drawn is CP, the color of frame buffer is CF, and the alpha value is A: C = CP x A + (1-A) x CF The alpha value is specified as 8-bit data. 00h means alpha value 0% and FFh means alpha value 100%. When the texture mapping function is enabled, the following blending modes can be selected: Normal Stencil Blends post texture mapping color with frame buffer color Uses MSB of texel color for ON/OFF control: MSB = 1: Texel color MSB = 0: Frame buffer color Stencil alpha Uses MSB of texel color for /OFF control: MSB = 1: Alpha blend texel color and current frame buffer color MSB = 0: Frame buffer color Note: MSB of frame buffer is drawn MSB of texel in both stencil and stencil alpha mode. Therefore in case MSB of texel is MSB=0, a color of frame buffer is frame buffer, but MSB of frame buffer is set to 0. MB86296S 112 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.5.3 Logic operation This mode executes a logic operation between the pixel to be drawn and the one already drawn in frame buffer and itsresult is drawn. Alpha blending cannot be used when this function is specified. Type CLEAR COPY NOP SET COPY INVERTED INVERT AND REVERSE OR REVERSE 0000 0011 0101 1111 1100 1010 0010 1011 ID Operation 0 S D 1 !S !D S & !D S | !D AND OR NAND NOR XOR EQUIV AND INVERTED OR INVERTED Type 0001 0111 1110 1000 0110 1001 0100 1101 ID S&D S|D ! (S & D) ! (S | D) S xor D ! (S xor D) !S & D !S | D Operation 10.5.4 Hidden plane management CORAL supports the Z buffer for hidden plane management. This function compares the Z value of a new pixel to be drawn and the existing Z value in the Z buffer. Display/not display is switched according to the Z-compare mode setting. Define the Z-buffer access options in the ZWRITEMASK mode. The Z compare operation type is determined by the Z compare mode. Either 16 or 8 bits can be selected for the Z-value. ZWRITEMASK Z Compare mode NEVER ALWAYS LESS LEQUAL EQUAL GEQUAL GREATER NOTEQUAL 1 0 000 001 010 011 100 101 110 111 Compare Z values, no Z value write overwrite Compare Z values, Z value write Never draw Always draw Draw if pixel Z value < current Z buffer value Draw if pixel Z value current Z buffer value Draw if pixel Z value = current Z buffer value Draw if pixel Z value current Z buffer value Draw if pixel Z value > current Z buffer value Draw if pixel Z value ! = current Z buffer value Code Condition MB86296S 113 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.6 Drawing Attributes 10.6.1 Line drawing attributes In drawing lines, the following attributes apply: Line Drawing Attributes Drawing Attribute Line width Broken line Anti-alias Description Line width selectable in range of 1 to 32 pixels Specify broken line pattern in 32-bit data Line edge smoothed when anti-aliasing enabled 10.6.2 Triangle drawing attributes In drawing triangles, the following attributes apply (these attributes are disabled in high-speed 2DTriangle). Texture mapping and tiling have separated texture attributes: Triangle Drawing Attributes Drawing Attribute Shading Alpha blending Alpha blending coefficient Description Gouraud shading or flat shading selectable In case of indirect color mode, gray scale gouraud shading is possible. Set alpha blending enabledisable per polygon / Set color blending ratio of alpha blending How to set gray scale gouraud shading 1. Set Frustum bit of GMDR0 register to 0. 2. Set identity matrix. 3. Set MDR2 register to the below. SM bit = 1, ZC bit = 0, ZW bit = 0, BM bit = 00, TT bit = 00 4. Set GG bit of MDR7 register to 1. 5. Execute drawing by same method as a direct color gouraud shading object. Note: - Please don't use G_BeginE command. - Please don't use floating data format in G_Vertex command. - R (red) parameter is used as a color parameter 6. Set GG bit of MDR7 register to 0 after rendering MB86296S 114 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.6.3 Texture attributes In texture mapping, the following attributes apply: Texture Attributes Drawing Attribute Texture mode Texture filter Texture coordinates correction Texture wrap Texture blend mode Bi-linear high-speed mode Description Select either texture mapping or tiling Select either point sampling or bi-linear filtering Select either linear or perspective correction Select either repeat or cramp of texture pattern Select either decal or modulate Texture data is created in a dedicated format to perform high-speed bi-linear filtering. MB86296S 115 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.6.4 BLT attributes In BLT drawing, the following attributes apply: BLT Attributes Drawing Attribute Logic operation mode Transparency mode Alpha map mode Description Specify two source logic operation mode Set transparent copy mode and transparent color Blend a color according to alpa map h 10.6.5 Character pattern drawing attributes Character Pattern Drawing Drawing Attribute Character pattern enlarge/shrink Character pattern color Transparency/non-transparency Description Vertical and Horizontal x 2, Horizontal x 2, Vertical and Horizontal x 1/2, Horizontal x 1/2 Set character color and background color Set background color to transparency/non-transparency MB86296S 116 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.7 Bold Line 10.7.1 Starting and ending points * * * In the CREMSON bold line mode, the starting and ending points are vertical to the principal axis. In the CORAL bold line mode, the starting and ending points are vertical to the theoretical line. Caution: CORAL line is generated by different algorithm. Thus drawing position is little bit different form other primitive. CREMSON bold line mode CORAL bold line mode MB86296S 117 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.7.2 Broken line pattern * * The broken line pattern vertical to the theoretical line (the CORAL broken line pattern) is supported. In the CREMSON bold line mode, lines can be drawn using the broken line pattern vertical to the CREMSON-compatible principal axis (the CREMSON broken line pattern), and can also be drawn using the CORAL broken line pattern. In the CORAL bold line mode, only the CORAL broken line pattern is supported. Broken line pattern made vertical * (1) (2) Starting point made vertical; ending point made vertical CORAL bold and broken lines Interpolation of broken line pattern Two types of interpolation modes are supported: * * No interpolation mode: Interpolation is not performed. Broken line pattern reference address fix mode: The same broken line pattern is referenced for several pixels before and after the joint of the bold line. Any pixel count can be set by the user. (1) (2) (1) (2) Edging not performed * Interpolation of bold line joint not performed * * Interpolation of broken line pattern reference performed Edging not performed * Interpolation of bold line joint not performed * Broken line pattern reference address fixed * MB86296S 118 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.7.3 Edging * * The edging line is supported. The line body and edging section can have depth information (Z offset). This mechanics makes it possible to easily represent a good connection of the overlaid part of the edging line. For example, when the line body depth information and edging section depth information are the same, the drawing result of the edging line is like the intersection shown in the figure below. Also, when the line body depth information and edging section depth information are different, the drawing result of the edging line is like the solid intersection shown in the figure below. Intersection Control by depth information Solid intersection Edging MB86296S 119 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.7.4 Interpolation of bold line joint * * * * In the bold line joint interpolation mode, the bold line joint is interpolated using a triangle as shown in the figure below. The edging line joint is also interpolated using a triangle, but the said depth information makes it possible to represent a good connection as shown in the figure below. Only LineStrip primitive can interpolate, and clipping sometimes breaks LineStrip. Caution: Sometime joint shape looks not perfect. (using approximate calculation) Interpolation using triangle Edging interpolation can also be performed. Interpolation of bold line joint MB86296S 120 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 10.8 Shadowing 10.8.1 Shadowing The Coral supports a shadow primitive which is same shape as a body. A shadow is drawn in a position shifted for a device coordinate(X, Y) by setting the OverlapXY command. And by setting the OverlapZ, it is possible to control a drawing result to avoid twice rendering in alpha blend or logical calculation. Two shadow lines are drawn in a line shadowing. One is a shadow line and another is a shadow composition line. A shadow composition line is used for avoiding an overlap with body line. And drawing priority can be set for rendering performance or anti-aliasing. A shadow primitive are drawn in a triangle and polygon shadowing. Drawing priority is fixed as a body primitive is first. - Line - Triangle and polygon Body line Shadow line Shadow composition line Body primitive Shadow primitive MB86296S 121 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 11 DISPLAY LIST 11.1 Overview Display list is a set of display list commands, parameters and pattern data. All display list commands stored in a display list are executed consequently. The display list is transferred to the display list FIFO by one of the following methods: * * * Write to display FIFO by CPU Transfer from main memory to display FIFO by external DMA Transfer from graphics memory to display FIFO by register setting Display list Command-1 Data 1-1 Data 1-2 Data 1-3 Display list Command-2 Data 2-1 Data 2-2 Data 2-3 Display List MB86296S 122 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 11.1.1 Header format The format of the display list header is shown below. Format List Format 1 Format 2 Format 3 Format 4 Format 5 Format 6 Format 7 Format 8 Format 9 Format 10 Format 11 Format 31 Type Type Type Type Type Type Type Type Type Type Type 24 23 Reserved Count Reserved Reserved Command Command Command Command Reserved Reserved Reserved 16 15 Count Reserved Address Reserved Reserved Reserved Count Reserved Reserved Reserved Count Reserved 0 Vertex Flag Vertex Flag Vertex Flag Vertex Description of Each Field Type Command Count Address Vertex Flag Display list type Command Count of data excluding header Address value used at data transfer Vertex number Attribute flag peculiar to display list command Vertex Number Specified in Vertex Code Vertex 00 01 10 11 Vertex number (Line) V0 V1 Setting prohibited Setting prohibited Vertex number (Triangle) V0 V1 V2 Setting prohibited 11.1.2 Parameter format The parameter format of the geometry command depends on the value set in the D field of GMDR0. When the D field is "00", all parameters are handled in the floating-point format. When the D field is "01", colors are handled as the packed RGB format, and others are handled as the fixed-point format. When the D field is "11", XY is handled as the packed integer format, colors are handled as the packed RGB format, and others are handled as the fixed-point format. In the following text, the floating-point format is suffixed by .float, the fixed point format is suffixed by .fixed, and the integer format is suffixed by .int. Set GMDR0 properly to match parameter suffixes. Rendering command parameters conform to the Coral-PA data format. MB86296S 123 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 11.2 Geometry Commands 11.2.1 Geometry command list CORAL geometry commands and each command code are shown in the table below. Type G_Nop G_Begin G_BeginE G_End G_EndE G_Vertex G_VertexLOG G_VertexNopLOG G_Init G_Viewport G_DepthRange G_LoadMatirix G_ViewVolumeXYClip G_ViewVolumeZClip G_ViewVolumeWClip OverlapXYOfft OverlapZOfft DC_LogOutAddr SetModeRegister SetGModeRegister SetColorRegister SetLVertex2i SetLVertex2iP Command See Geometry command code table (1)(2). See Geometry command code table (3)(4). No operation Specifies primitive type and pre-processes Specifies primitive type and pre-processes This command is used at execution of the CORAL extended function. Ends primitive This command is used at execution of G_Begin Ends primitive This command is used at execution of G_BeginE Sets vertex parameter and draws Sets vertex parameter and draws Outputs device coordinates Only outputs device coordinates Initialize geometry engine Scale to screen coordinates (X, Y) and set origin offset Scale to screen coordinates (Z) and set origin offset Load geometric transformation matrix Set boundary value (X, Y) of view volume clip Set boundary value (Z) of view volume clip Set boundary value (W) of view volume clip Sets XY offset at shading Sets Z offset of shade primitive; sets Z offset of edge primitive; sets Z offset of interpolation primitive at 2D drawing with top-left nonapplicable Sets starting address of device coordinates output Sets drawing extended mode register Sets geometry extended mode register Sets body color, shade color, and edge color Pass through high-speed 2DLine drawing register Pass through high-speed 2DLine drawing register Description See Command table. See Command table. See Command table. See Command table. See Command table. MB86296S 124 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Type code table Type G_Nop G_Begin G_End G_Vertex G_VertexLOG G_VertexNopLOG G_Init G_Viewport G_DepthRange G_LoadMatirix G_ViewVolumeXYClip G_ViewVolumeZClip G_ViewVolumeWClip SetLVertex2i SetLVertex2iP SetModeRegister SetGModeRegister OverlapXY0fft OverlapZ0fft DC_LogOutAddr SetColorRegister G_BeginE G_EndE 0010_0000 0010_0001 0010_0011 0011_0000 0011_0010 0011_0011 0100_0000 0100_0001 0100_0010 0100_0011 0100_0100 0100_0101 0100_0110 0111_0010 0111_0011 1100_0000 1100_0001 1100_1000 1100_1001 1100_1100 1100_1110 1110_0001 1110_0011 Code MB86296S 125 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Geometry command code table GMDR0.FX bit is expanded for CORAL-PA. Work Only for G_Begin/Triangle(s,_Strip,_Fan) (1) Integer setup type (for G_Begin) In setup processing, "XY" is calculated in the integer format and other parameters are calculated in the floating-point format. (*.int) or In setup processing, "XY" is calculated in the floating-point format and other parameters are calculated in the floating-point format. (*.float) Code Command(GMDR0.FX==0) Command(GMDR0.FX==1) 0001_0000 0001_0001 0001_0010 0001_0011 0001_0101 0001_0111 0001_1000 Points.int Lines.int Polygon.int Triangles.int Line_Strip.int Triangle_Strip.int Triangle_Fan.int Points.int Lines.int Polygon.int Triangles.float Line_Strip.int Triangle_Strip.float Triangle_Fan.float (2) "Unclipped" integer setup type(for G_Begin) This command does not clip the view volume. Only "XY" is enabled as the input parameter. In setup processing, "XY" is calculated in the integer format. (*.int) The screen projection (GMDR0[0]=1) performed using this command is not assured. GMDR0.FX has no mean for nclip Code 0011_0000 0011_0001 0011_0010 0011_0011 0011_0101 0011_0111 0011_1000 Command(GMDR0.FX==0) nclip_Points.int nclip_Lines.int nclip_Polygon.int nclip_Triangles.int nclip_Line_Strip.int nclip_Triangle_Strip.int nclip_Triangle_Fan.int nclip_Points.int nclip_Lines.int nclip_Polygon.int nclip_Triangles.int nclip_Line_Strip.int nclip_Triangle_Strip.int nclip_Triangle_Fan.int Command(GMDR0.FX==1) MB86296S 126 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL (3) Integer setup type (for G_BeginE) In setup processing, "XY" is calculated in the integer format and other parameters are calculated in the floating-point format. (GMDR0.FX has no mean for G_BeginE) Code 0001_0000 0001_0001 0001_0010 0001_0011 0001_0101 0001_0111 0001_1000 Command(GMDR0.FX==0) Points.int Lines.int Polygon.int Triangles.int Line_Strip.int Triangle_Strip.int Triangle_Fan.int Points.int Lines.int Polygon.int Triangles.int Line_Strip.int Triangle_Strip.int Triangle_Fan.int Command(GMDR0.FX==1) (4) "Unclipped" integer setup type(for G_BeginE) This command does not clip the view volume. Only "XY" is enabled as the input parameter. In setup processing, "XY" is calculated in the integer format. The screen projection (GMDR0[0]=1) performed using this command is not assured. (GMDR0.FX has no mean for G_BeginE) Code 0011_0000 0011_0001 0011_0010 0011_0011 0011_0101 0011_0111 0011_1000 Command(GMDR0.FX==0) nclip_Points.int nclip_Lines.int nclip_Polygon.int nclip_Triangles.int nclip_Line_Strip.int nclip_Triangle_Strip.int nclip_Triangle_Fan.int nclip_Points.int nclip_Lines.int nclip_Polygon.int nclip_Triangles.int nclip_Line_Strip.int nclip_Triangle_Strip.int nclip_Triangle_Fan.int Command(GMDR0.FX==1) MB86296S 127 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 11.2.2 Explanation of geometry commands G_Nop (Format 1) 31 No operation G_Nop 24 23 Reserved 16 15 Reserved 0 G_Init (Format 1) 31 The G_Init command initializes geometry engine. Execute this command before processing. _ G_Init 24 23 Reserved 16 15 Reserved 0 G_End (Format 1) 31 The G_End command ends one primitive. The G_Vertex command must be specified between the G_Begin command and G_End command. G_End 24 23 Reserved 16 15 Reserved 0 MB86296S 128 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL G_Begin (Format 5) 31 24 23 16 15 0 The G_Begin command sets types of primitive for geometry processing and drawing. A vertex is set and drawn by the G_Vertex command. The G_Vertex command must be specified between the G_Begin command and G_End command. Only G_Vertex or SetRegister for FC/BC (XY Only vertex) can placed between G_Begin and G_Begin Command Reserved G_End. Command: Points* Lines* Polygon* Triangles* Line_Strip* Triangle_Strip* Triangle_Fan* Handles primitive as point Handles primitive as independent line Handles primitive as polygon Handles primitive as independent triangle Handles primitive as line strip Handles primitive as triangle strip Handles primitive as triangle fan Usable combinations of GMDR0 mode setting and primitives are as follows: Unclipped primitives (nclip*) (ST,Z,C) Point Line Triangle Polygon (0,0,0) Other than above x x x x Primitives other than unclipped primitives (ST,Z,C) Point (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,x,x) Line Triangle Polygon x x x x x x x x x x MB86296S 129 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL G_BeginE (Format 5) 31 24 23 16 15 0 This is the extended G_Begin command. When using the following functions, this command must be executed instead of G_Begin. * * G_Begin Command Reserved Mode register(MDR1S/MDR1B/MDR1TL/MDR2S/MDR2TL/GMDR1E/GMDR2E) Log output of device coordinates G_VertexLOG/G_VertexNopLOG Polygon with Z or texture The G_BeginE command sets types of primitive for geometry processing and drawing. Vertex setting/drawing using the above extended function is performed using the G_Vertex* command. The G_Vertex* command must be set between the G_BeginE command and the G_EndE command. Only G_Vertex/G_VertexLOG/G_VertexNopLOG or SetColorRegister(XY only vertex) or OverLapZofft can placed between G_BeginE and G_EndE. Command: Points* Lines* Handles primitive as point Handles primitive as independent line * Polygon* Triangles* Line_Strip* Triangle_Strip* Triangle_Fan* Interpolation of the joint and broken line pattern is not supported. Handles primitive as polygon Handles primitive as independent triangle Handles primitive as line strip Handles primitive as triangle strip Handles primitive as triangle fan Usable combinations of GMDR0 mode setting and primitives are as follows: Unclipped primitives (nclip*) (ST,Z,C) Point Line Triangle Polygon (0,0,0) Other than above x x Line x Triangle x Polygon(*2) Primitives other than unclipped primitives (ST,Z,C) Point (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,x,x) x x x x x x x (*1) x *1: Shading is not assured. *2: In case of drawing polygon with Z,ST=1, the algorithm is approximate calculation. The triangle algorithm is more accurate. MB86296S FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL G_Vertex/G_VertexLOG/G_VertexNopLOG (Format 1) When data format is floating-point format 31 G_Vertex 24 23 Reserved 16 15 X.float Y.float Z.float R.float G.float B.float S.float T.float 16 15 Reserved 0 When data format is fixed-point format 31 G_Vertex A.int 24 23 Reserved R.int X.fixed Y.fixed Z.fixed S.fixed T.fixed 16 15 Reserved G.int B.int 0 When data format is packed integer format 31 G_Vertex A.int 24 23 Y.int Reserved R.ing Z.fixed S.fixed T.fixed Reserved X.int G.int B.int 0 The G_Vertex command sets vertex parameters and processes and draws the geometry of the primitive specified by the G_Begin* command. Note the following when using this command: * Required parameters depend on the setting of the GMDR0 register. Proper values must be set as the mode values of the MDR0 to MDR4 registers to be finally reflected at drawing. That is, when "Z" comparison is made (ZC bit of MDR1 or MDR2 = 1), the Z bit of the GMDR0 register must be set to 1. When Gouraud shading is performed (SM bit of MDR2 = 1), the C bit of the GMDR0 register must be set to 1. When texture mapping is performed (TT bits of MDR2 = 10), the ST bit of the GMDR0 register must be set to 1. When the Z bit of the GMDR0 register is 0, input "Z" (Zoc) is treated as "0". Use values normalized to 0 and 1 as texture coordinates (S, T). When the color RGB is floating-point format, use values normalized to 0 and 1 as the 8-bit color value. For the packed RGB, use the 8-bit color value directly. The GMDR1 register is valid only for line drawing; it is ignored in primitives other than line. The GMDR2 register matters only when a triangle (excluding a polygon) is drawn. At primitives other than triangle, set "0". The use of both G_BeginE to G_EndE, and G_VertexLOG/NopLOG is not assured. * * * * * * MB86296S 131 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL * * * G_VertexNopLOG, except for the primitive as point is not assured. A vertex data is processed at every time. For example, the Coral draws interpolation of bold line joint, edging line, shadows at every vertices. Alpha parameter can be provided only packed ARGB format. G_Viewport (Format 1) 31 G_Viewport 24 23 The G_Viewport command sets the "X,Y" scale/offset value used when normalized device coordinates (NDC) is transformed into device coordinates (DC). Reserved X_Scaling.float/fixed X_Offset.float/fixed Y_Scaling.float/fixed Y_Offset.float/fixed 16 15 Reserved 0 G_DepthRange (Format 1) 31 G_DepthRange 24 23 The G_DepthRange command sets the "Z" scale/offset value used when an NDC is transformed into a DC. Reserved Z_Scaling.float/fixed Z_Offset.float/fixed 16 15 Reserved 0 G_LoadMatrix (Format 1) 31 G_LoadMatrix 24 23 The G_LoadMatrix command sets the transformation matrix used when object coordinates (OC) is transformed into clip coordinates (CC). Reserved Matrix_a0.float/fixed Matrix_a1.float/fixed Matrix_a2.float/fixed Matrix_a3.float/fixed Matrix_b0.float/fixed Matrix_b1.float/fixed Matrix_b2.float/fixed Matrix_b3.float/fixed Matrix_c0.float/fixed Matrix_c1.float/fixed Matrix_c2.float/fixed Matrix_c3.float/fixed Matrix_d0.float/fixed Matrix_d1.float/fixed Matrix_d2.float/fixed Matrix_d3.float/fixed 16 15 Reserved 0 MB86296S 132 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL G_ViewVolumeXYClip (Format 1) 31 24 23 16 15 0 G_ViewVolumeXYClip The G_ViewVolumeXYClip command sets the X,Y coordinates of the clip boundary value in view volume clipping. Reserved XMIN.float/fixed XMAX.float/fixed YMIN.float/fixed YMAX.float/fixed Reserved G_ViewVolumeZClip (Format 1) 31 G_ViewVolumeZClip 24 23 The G_ViewVolumeZClip command sets the Z coordinates of the clip boundary value in view volume clipping. Reserved ZMIN.float/fixed ZMAX.float/fixed 16 15 Reserved 0 G_ViewVolumeWClip (Format 1) 31 G_ViewVolumeWClip 24 23 The G_ViewVolumeWClip command sets the W coordinates of the clip boundary value in view volume clipping (minimum value only). Reserved WMIN.float/fixed 16 15 Reserved MB86296S 133 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL OverlapXYOfft (Format5) 31 OverlapXYOfft 24 23 Y Offset 16 15 0 Command The OverlapXYOfft command sets the XY offset of the shade primitive relative to the body primitive at shading drawing. Shadow shape is same as body. Command: Command ShadowXY Code Explanation 0000_0000 ShadowXY command sets the XY offset of the shade primitive relative to the body primitive. ShadowXYcompsition 0000_0001 ShadowXYcomposition command sets the XY offset of the shade synthetic primitive relative to the body primitive. It command synthesizes a shade from the relationship between the XY offset set using ShadowXY and this XY offset. This command is enabled for only lines. 31 24 23 don't care 24 23 16 15 0 Reserved X Offset OverlapZOfft (Format5) OverlapZOfft Command Reserved Z Offset Note: When MDR0 ZP = 1, only lower 8 bits are enabled. 31 OverlapZOfft S_Z Offset Packed_ONBS B_Z Offset 16 15 N_Z Offset Reserved 0 O_Z Offset The OverlapZOfft command sets the Z offset of the shade primitive relative to the body primitive, sets the Z-offset of the edge primitive relative to the body primitive, and sets the Z offset of the interpolation primitive relative to the body primitive, with the top-left rule non-applicable in effect. At this time, the following relationship must be satisfied when, for example, GREATER is specified for the Z value comparison mode: Body primitive > Top-left rule non-applicable interpolation primitive > Edge primitive > Shade primitive Command: Command Origin Code Explanation 0000_0000 Origin command sets the Z offset of the body primitive. When drawing one primitive below the other primitive (for example, when drawing a solid intersection), this Z offset is changed. When drawing an ordinary intersection, set the same Z offset as other primitives. 0000_0001 NonTopLeft command sets the Z offset of the interpolation primitive, with the top-left non applicable. 0000_0010 Border command sets the Z offset of the edge primitive. 0000_0011 Shadow command sets the Z offset of the shade primitive. 0000_0111 Packed_ONBS command sets the above four types of Z offsets. NonTopLeft Border Shadow Packed_ONBS MB86296S 134 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DC_LogOutAddr (Format5) 31 OverlapXYOfft 000000 24 23 16 15 LogOutAddr 0 Command Reserved The DC_LogOutAddr command sets the starting address of the log output destination of the device coordinates. SetModeRegister (Format5) 31 SetModeRegister 24 23 Command 16 15 MDR1*/MDR2* Reserved 0 The SetModeRegister command sets the mode register for shade primitive, for edge primitive, and for top-left non-applicable primitive. At drawing of these primitives, also set the mode register (MDR1/MDR2) for the body primitive, using this packet. Command: Command MDR1 MDR1S MDR1B MDR2 MDR2S MDR2LT Code 0000_0000 0000_0010 0000_0100 0000_0001 0000_0011 0000_0111 Explanation MDR1 command sets MDR1 for the body primitive. MDR1S command sets MDR1 for the shade primitive. MDR1B command sets MDR1 for the edge primitive. MDR2 command sets MDR2 for the body primitive. MDR2S command sets MDR2 for the shade primitive. MDR2LT command sets MDR2 for the top-left nonapplicable primitive. - SetGModeRegister (Format5) 31 SetGModeRegister 24 23 16 15 Command GMDR1E/GMDR2E Reserved 0 The SetGModeRegister command sets the geometry extended mode register. Command: Command GMDR1E GMDR2E Code 0001_0000 0010_0000 Explanation GMDR1E command sets GMDR1E and at the same time, updates GMDR1. GMDR2E command sets GMDR2E and at the same time, updates GMDR2. MB86296S 135 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL SetColorRegister (Format5) 31 SetColorRegister 24 23 16 15 FGC8/16/24 0 Command Reserved The SetColorRegister command sets the foreground color and background color of the body primitive, shade primitive, and edge primitive. Commands: Command ForeColor BackColor ForeColorShadow BackColorShadow ForeColorBorder BackColorBorder Code 0000_0000 0000_0001 0000_0010 0000_0011 0000_0100 0000_0101 Explanation ForeColor command sets the foreground color for the body primitive. BackColor command sets the background color for the body primitive. ForeColorShadow command sets the foreground color for the shade primitive. BackColorShadow command sets the background color for the shade primitive. ForeColorBorder command sets the foreground color for the edge primitive. BackColorBorder command sets the background color for the edge primitive. SetRegister (Format 2) 31 SetRegister 24 23 Count 16 15 (Val 0) (Val 1) ... (Val n) Address 0 The SetRegister command is upper compatible with CREMSON SetRegister. It can specify the address of a register in the geometry engine. SetLVertex2i (Format 1) 31 SetLVertex2i 24 23 Reserved 16 15 LX0dc LY0dc Reserved 0 The SetLVertex2i command issues the SetRegister_LXOdc/LYOdc command (MB86290A command to set starting vertex at line drawing) in the geometry FIFO interface. This performs processing faster than when the SetRegister_LXOdc/LYOdc command is input directly to the geometry FIFO. SetLVertex2iP (Format 1) 31 SetLVertex2iP 24 23 LY0dc Reserved 16 15 Reserved LX0dc 0 The SetLVertex2iP command supports packed XY of SetLVertex21. MB86296S 136 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 11.3 Rendering Command 11.3.1 Command list The following table lists CORAL rendering commands and their command codes. Type Nop Interrupt Sync SetRegister SetVertex2i Draw DrawPixel DrawPixelZ DrawLine Command Description Normal PolygonBegin PolygonEnd Flush_FB/Z Pixel PixelZ Xvector Yvector AntiXvector AntiYvector ZeroVector OneVector TrapRight TrapLeft TriangleFan FlagTriangleFan BltFill ClearPolyFlag BltDraw Bitmap BltDraw TopLeft TopRight BottomLeft BottomRight LoadTexture LoadTILE LoadTexture LoadTILE DrawLine2i DrawLine2iP DrawTrap DrawVertex2i DrawVertex2iP DrawRectP DrawBitmapP DrawBitmapLargeP BltCopyP BltCopyAlternateP LoadTextureP BltTextureP BltCopyAltAlphaBlendP No operation Interrupt request to host CPU Synchronization with events Sets data to register Sets data to high-speed 2DTriangle vertex register Initializes border rectangle calculation of multiple vertices random shape Clears polygon flag after drawing polygon Flushes drawing pipelines Draws point Draws point with Z Draws line (principal axis X) Draws line (principal axis Y) Draws line with anti-alias option (principal axis X) Draws line with anti-alias option (principal axis Y) Draws high-speed 2DLine (with vertex 0 as starting point) Draws high-speed 2DLine (with vertex 1 as starting point) Draws right triangle Draws left triangle Draws high-speed 2DTriangle Draws high-speed 2DTriangle for multiple vertices random shape Draws rectangle with single color Clears polygon flag buffer Draws Blt (16-bit) Draws binary bit map (character) Draws Blt (32-bit) Blt transfer from top left coordinates Blt transfer from top right coordinates Blt transfer from bottom left coordinates Blt transfer from bottom right coordinates Loads texture pattern Loads tile pattern Loads texture pattern from local memory Loads tile pattern from local memory Alpha blending is supported (see the alpha map). BltCopyAlternateP MB86296S 137 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Type Code Table Type DrawPixel DrawPixelZ DrawLine DrawLine2i DrawLine2iP DrawTrap DrawVertex2i DrawVertex2iP DrawRectP DrawBitmapP BitCopyP BitCopyAlternateP LoadTextureP BltTextureP BltCopyAltAlphaBlendP SetVertex2i SetVertex2iP Draw SetRegister Sync Interrupt Nop 0000_0000 0000_0001 0000_0010 0000_0011 0000_0100 0000_0101 0000_0110 0000_0111 0000_1001 0000_1011 0000_1101 0000_1111 0001_0001 0001_0011 0001_1111 0111_0000 0111_0001 1111_0000 1111_0001 1111_1100 1111_1101 1111_1111 Code MB86296S 138 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Command Code Table (1) Command Pixel PixelZ Xvector Yvector XvectorNoEnd YvectorNoEnd XvectorBlpClear YvectorBlpClear XvectorNoEndBlpClear YvectorNoEndBlpClear AntiXvector AntiYvector AntiXvectorNoEnd AntiYvectorNoEnd AntiXvectorBlpClear AntiYvectorBlpClear AntiXvectorNoEndBlpClear AntiYvectorNoEndBlpClear ZeroVector Onevector ZeroVectorNoEnd OnevectorNoEnd ZeroVectorBlpClear OnevectorBlpClear ZeroVectorNoEndBlpClear OnevectorNoEndBlpClear AntiZeroVector AntiOnevector AntiZeroVectorNoEnd AntiOnevectorNoEnd AntiZeroVectorBlpClear AntiOnevectorBlpClear AntiZeroVectorNoEndBlpClear AntiOnevectorNoEndBlpClear 000_00000 000_00001 001_00000 001_00001 001_00010 001_00011 001_00100 001_00101 001_00110 001_00111 001_01000 001_01001 001_01010 001_01011 001_01100 001_01101 001_01110 001_01111 001_10000 001_10001 001_10010 001_10011 001_10100 001_10101 001_10110 001_10111 001_11000 001_11001 001_11010 001_11011 001_11100 001_11101 001_11110 001_11111 Code MB86296S 139 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Command Code Table (2) Command BltFill BltDraw Bitmap TopLeft TopRight BottomLeft BottomRight LoadTexture LoadTILE TrapRight TrapLeft TriangleFan FlagTriangleFan Flush_FB Flush_Z PolygonBegin PolygonEnd ClearPolyFlag Normal 010_00001 010_00010 010_00011 010_00100 010_00101 010_00110 010_00111 010_01000 010_01001 011_00000 011_00001 011_00010 011_00011 110_00001 110_00010 111_00000 111_00001 111_00010 111_11111 Code MB86296S 140 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 11.3.2 Details of rendering commands All parameters belonging to their command are stored in relevant registers. The definition of each parameter is explained in the section of each command. Nop (Format1) 31 No operation 31 Nop 24 23 Reserved 16 15 Reserved 0 Interrupt (Format1) Interrupt 24 23 The Interrupt command generates interrupt request to host CPU. Reserved 16 15 Reserved 0 Sync (Format9) 31 The Sync command suspends all subsequent display list processing until event set in flag detected. Flag: Bit number 4 3 2 1 Bit field name Reserved Reserved Reserved Reserved VBLANK VBLANK Synchronization 0 No operation 1 Wait for VSYNC detection 0 VBLANK Bit 0 Sleep 24 23 Reserved 16 15 Reserved 4 flag 0 MB86296S 141 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL SetRegister (Format2) 31 24 23 16 15 0 SetRegister Count (Val 0) (Val 1) (Val n) Address The SetRegister command sets data to sequential registers. Count: Data word count (in double-word unit) Register address Address: Set the value of the address for SetRegister given in the register list. When transferring two or more data, set the starting register address. SetVertex2i (Format8) 31 SetVertex2i 24 23 The SetVertex2i command sets vertices data for high-speed 2DLine or high-speed 2DTriangle to registers. Commands: Normal PolygonBegin Sets vertex data (X, Y). Starts calculation of circumscribed rectangle for random shape to be drawn. Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd. Xdc Ydc Command 16 15 Reserved 43210 flag vertex Flag: Not used SetVertex2iP (Format8) 31 SetVertex2i 24 23 The SetVertex2iP command sets vertices data for high-speed 2DLine or high-speed 2DTriangle to registers. Only the integer (packed format) can be used to specify these vertices. Commands: Normal PolygonBegin Sets vertices data. Starts calculation of circumscribed rectangle of random shape to be drawn. Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd. Ydc Command 16 15 Reserved 43210 Xdc flag vertex Flag: Not used MB86296S 142 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Draw (Format5) 31 24 23 16 15 0 The Draw command executes drawing command. All parameters required for drawing command execution must be set at their appropriate registers. Commands: PolygonEnd Draws polygon end. Fills random shape with color according to flags generated by FlagTriangleFan command and information of circumscribed rectangle generated by PolygonBegin command. Flushes drawing data in the drawing pipeline into the graphics memory. Place this command at the end of the display list. Flushes Z value data in the drawing pipeline into the graphics memory. When using the Z buffer, place this command together with the Flush_FB command at the end of the display list. 24 23 PXs PYs 16 15 0 Draw Command Reserved Flush_FB Flush_Z DrawPixel (Format5) 31 DeawPixel Command Reserved The DrawPixel command draws pixel. Command: Pixel Draws pixel without Z value. DrawPixelZ (Format5) 31 DeawPixel 24 23 The DrawPixelZ command draws pixel with Z value. Command: PixelZ Draws pixel with Z value. PXs PYs PZs Command 16 15 Reserved MB86296S 143 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DrawLine (Format5) 31 24 23 16 15 0 DrawLine Command The DrawLine command draws line. It starts drawing after setting all parameters at line draw registers. Commands: Xvector Yvector XvectorNoEnd YvectorNoEnd XvectorBlpClear Draws line (principal axis X). Draws line (principal axis Y). Draws line (principal axis X, and without end pointdrawing ). Draws line (principal axis Y, and without end point drawing). Draws line (principal axis X, and prior to drawing, broken line pattern reference position cleared). YvectorBlpClear Draws line (principal axis Y, and prior to drawing, broken line pattern reference position cleared). XvectorNoEndBlpClear Draws line (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). YvectorNoEndBlpClear Draws line (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiXvector Draws anti-alias line (principal axis X). AntiYvector Draws anti-alias line (principal axis Y). AntiXvectorNoEnd Draws anti-alias line (principal axis X, and without end point drawing). AntiYvectorNoEnd Draws anti-alias line (principal axis Y, and without end point drawing). AntiXvectorBlpClear Draws anti-alias line (principal axis X and prior to drawing, broken line pattern reference position cleared). AntiYvectorBlpClear Draws anti-alias line (principal axis Y and prior to drawing, broken line pattern reference position cleared). AntiXvectorNoEndBlpClear Draws anti-alias line (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiYvectorNoEndBlpClear Draws anti-alias line (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). LPN LXs LXde LYs LYde Reserved MB86296S 144 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DrawLine2i (Format7) 31 24 23 16 15 0 DrawLine2i The DrawLine2i command draws high-speed 2DLine. It starts drawing after setting parameters at the high-speed 2DLine drawing registers. Integer data can only be used for coordinates. Commands: ZeroVector OneVector ZeroVectorNoEnd Draws line from vertex 0 to vertex 1. Draws line from vertex 1 to vertex 0. Draws line from vertex 0 to vertex 1 (without drawing end point). OneVectorNoEnd Draws line from vertex 1 to vertex 0 (without drawing end point). ZeroVectorBlpClear Draws line from vertex 0 to vertex 1 (principal axis X, and prior to drawing, broken line pattern reference position cleared). OneVectorBlpClear Draws line from vertex 1 to vertex 0 (principal axis Y, and prior to drawing, broken line pattern reference position cleared). ZeroVectorNoEndBlpClear Draws line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). OneVectorNoEndBlpClear Draws line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiZeroVector Draws anti-alias line from vertex 0 to vertex 1. AntiOneVector Draws anti-alias line from vertex 1 to vertex 0. AntiZeroVectorNoEnd Draws anti-alias line from vertex 0 to vertex 1 (without end point). AntiOneVectorNoEnd Draws anti-alias line from vertex 1 to vertex 0 (without end point). AntiZeroVectorBlpClear Draws anti-alias line from vertex 0 to vertex 1 (principal axis X and prior to drawing, broken line pattern reference position cleared). AntiOneVectorBlpClear Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y and prior to drawing, broken line pattern reference position cleared). AntiZeroVectorNoEndBlpClear Draws anti-alias line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiOneVectorNoEndBlpClear Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). LFXs LFYs Command Reserved 0 0 vertex MB86296S 145 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DrawLine2iP (Format7) 31 24 23 16 15 0 DrawLine2iP The DrawLine2iP command draws high-speed 2DLine. It starts drawing after setting parameters at high-speed 2DLine drawing registers. Only packed integer data can be used for coordinates. Commands: ZeroVector OneVector ZeroVectorNoEnd Draws line from vertex 0 to vertex 1. Draws line from vertex 1 to vertex 0. Draws line from vertex 0 to vertex 1 (without drawing end point). OneVectorNoEnd Draws line from vertex 1 to vertex 0 (without drawing end point). ZeroVectorBlpClear Draws line from vertex 0 to vertex 1 (principal axis X, and prior to drawing, broken line pattern reference position cleared). OneVectorBlpClear Draws line from vertex 1 to vertex 0 (principal axis Y, and prior to drawing, broken line pattern reference position cleared). ZeroVectorNoEndBlpClear Draws line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). OneVectorNoEndBlpClear Draws line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiZeroVector Draws anti-alias line from vertex 0 to vertex 1. AntiOneVector Draws anti-alias line from vertex 1 to vertex 0. AntiZeroVectorNoEnd Draws anti-alias line from vertex 0 to vertex 1 (without end point). AntiOneVectorNoEnd Draws anti-alias line from vertex 1 to vertex 0 (without end point). AntiZeroVectorBlpClear Draws anti-alias line from vertex 0 to vertex 1 (principal axis X and prior to drawing, broken line pattern reference position cleared). AntiOneVectorBlpClear Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y and prior to drawing, broken line pattern reference position cleared). AntiZeroVectorNoEndBlpClear Draws anti-alias line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiOneVectorNoEndBlpClear Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). LFYs Command Reserved LFXs vertex MB86296S 146 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DrawTrap (Format5) 31 24 23 16 15 0 DrawTrap Ys Command The DrawTrap command draws Triangle. It starts drawing after setting parameters at the Triangle Drawing registers (coordinates). Commands: TrapRight TrapLeft Draws right triangle. Draws left triangle. USN LSN Xs DXdy XUs DXUdy XLs DXLdy Reserved 0 0 0 DrawVertex2i (Format7) 31 DrawVertex2i 24 23 The DrawVertex2i command draws high-speed 2DTriangle It starts triangle drawing after setting parameters at 2DTriangle Drawing registers. Commands: TriangleFan FlagTriangleFan Xdc Ydc Command 16 15 Reserved 0 0 vertex 0 Draws high-speed 2DTriangle. Draws high-speed 2DTriangle for polygon drawing in the flag buffer. DrawVertex2iP (Format7) 31 DrawVertex2iP 24 23 The DrawVertex2iP command draws high-speed 2DTriangle It starts drawing after setting parameters at 2DTriangle Drawing registers Only the packed integer format can be used for vertex coordinates. Commands: TriangleFan FlagTriangleFan Ydc Command 16 15 Reserved Xdc vertex 0 Draw high-speed 2DTriangle. Draws high-speed 2DTriangle for polygon drawing in the flag buffer. MB86296S 147 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DrawRectP (Format5) 31 24 23 16 15 0 DrawRectP The DrawRectP command fills rectangle. The rectangle is filled with the current color after setting parameters at the rectangle registers. Please set XRES(X resolution) to in 8 byte units when using this command. Commands: BltFill ClearPolyFlag Fills rectangle with current color (single). Fills polygon drawing flag buffer area with 0. The size of drawing frame is defined in RsizeX,Y. RYs RsizeY Command Reserved RXs RsizeX DrawBitmapP (Format6) 31 DrawBitmapP 24 23 RYs RsizeY Command 16 15 (Pattern 0) (Pattern 1) (Pattern n) Count RXs RsizeX 0 The DrawBitmapP command draws rectangle patterns. Please set XRES(X resolution) to in 8 byte units when using this command. Commands: BltDraw DrawBitmap Draws rectangle of 8 bits/pixel or 16 bits/pixel. Draws binary bitmap character pattern. Bit 0 is drawn in transparent or background color, and bit 1 is drawn in foreground color. DrawBitmapLargeP (Format11) 31 DrawBitmapLargeP 24 23 Command 16 15 Rys RsizeY Count (Pattern 0) (Pattern 1) (Pattern n) Reserved Rxs RsizeX 0 The DrawBitmapP command draws rectangle patterns. The parameter(count field) could be used up to 32-bit(*1) unlike DrawBitmapP. (*1: The data format of counter field is signed long. Thus actually it is possible to use up to 31-bit.) Please set XRES(X resolution) to in 8 byte units when using this command. Commands: BltDraw Draws rectangle of 8 bits/pixel or 16 bits/pixel. MB86296S 148 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL BltCopyP (Format5) 31 24 23 16 15 0 BltCopyP The BltCopyP command copies rectangle pattern within drawing frame. Please set XRES(X resolution) to in 8 byte units when using this command. Commands: TopLeft TopRight BottomLeft BottomRight 31 SRYs DRYs BRsizeY Command Reserved SRXs DRXs BRsizeX Starts BitBlt transfer from top left coordinates. Starts BitBlt transfer from top right coordinates. Starts BitBlt transfer from bottom left coordinates. Starts BitBlt transfer from bottom right coordinates. Command 16 15 BltCopyAlternateP (Format5) BltCopyAlternateP 24 23 SRYs DRYs BRsizeY SADDR SStride DADDR DStride Reserved SRXs DRXs BRsizeX 0 The BltCopyAlternateP command copies rectangle between two separate drawing frames. Please set XRES(X resolution) to in 8 byte units when using this command. And please set SStride and DStride to in 8 byte units. Command: TopLeft Starts BitBlt transfer from top left coordinates. MB86296S 149 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL BltCopyAltAlphaBlendP (Format5) 31 BltCopyAlternateP 24 23 Command 16 15 SRYs BlendRYs DRYs BRsizeY SADDR SStride BlendStride Reserved SRXs BlendRXs DRXs BRsizeX 0 The BltCopyAltAlphaBlendP command performs alpha blending for the source (specified using SADDR, SStride, SRXs, SRXy) and the alpha map (specified using ABR (alpha base address), BlendStride, BlendRXs, BlendRYs) and then copies the result of the alpha blending to the destination (specified using FBR (frame buffer base address), XRES (X resolution), DRXs, and DRYs). Please set XRES(X resolution) to in 8 byte units when using this command. And please set SStride and BlendStride to in 8 byte units. Command: reserved Set 0000_0000 to maintain future compatibility. MB86296S 150 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 12. PCI Configuration Registers For the Coral-PA, the PCI Configuration registers are divided into two subgroups: 1. Device specific registers (eg. Vendor ID). These should not normally be modified by the user. These registers can be loaded from EEPROM. 2. Application specific registers (eg. PCI Command Register). These can be modified by the user and must be programmed using PCI Configuration cycles as they can not be loaded from the EEPROM. However an EEPROM loadable 32 bit register is available for the user. For the EEPROM loadable configuration registers, the Coral-PA uses Byte Addresses which are used on the PCI bus. However, when in 16 bit data mode the EEPROM requires word addresses. The EEPROM preloaded using the 16 bit word addresses shown in the below. 12.1 PCI Configuration register list 31:24 23:16 15:8 7:0 VENDER ID COMMND REVISION ID MASTER CACHELINE LATENCY SIZE TIMER BASE ADDRESS REGISTER0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SUBSYSTEM ID SUBSYSTEM VENDOR ID RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED MAX LAT MIN GNT INTERRUPT INTERRUPT PIN LINE RESERVED RETRY TRDY TIME OUT TIME OUT USER REGISTER DEVICE ID STATUS CLASS CODE BIST HEADER TYPE PCI Byte Address 00 04 08 0C EEPROM Word Address 01 05 07 00 04 - 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 17 1F 23 16 1E 22 MB86296S 151 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 12.2 PCI Configuration Registers Descriptions In the following sections, the following abbreviations in the "Type" field apply: RORegister is Read -only, not loadable via EEPROM. : ER: Register is Read-only, loadable via EEPROM. RW: Register is Read/Writable using PCI configuration transactions; not loadable via EEPROM. For further information about these fields, please refer to the PCI Specification v2.1, Section6. Vendor ID Register Bit 15-0 Type ER Reset Value 10CFh Description Identifies the vendor of the IC. The Reset Value represents the vendor ID of Fujitsu Limited. Device ID Register Bit 15-0 Type ER Reset Value 201Eh Description ID of Fujitsu Limited PCI device (Coral device ID). PCI Command Register Bit 15-10 9 8 7 6 5 4 Type RW RW RW RW Reset Value 0 0 0 0 0 0 0 3 2 1 0 RW RW RW 0 0 0 0 Reserved Fast Back-to-Back Master Enable. This is not supported by the Coral-PA and should be set to `0' System Error Enable. This is supported by the Coral-PA. Reserved Parity Error Enable. This is supported by the Coral-PA. Reserved Memory Write and Invalidate Enable. This feature is not supported in master mode, but in slave mode the Coral-PA will convert any Memory Write and Invalidate commands to Memory Write commands. This bit should be set to `0'. Reserved Bus Master Enable. This bit must be set to `1' by the user for correct operation. Memory Access Enable. This bit must be set to `1' by the user for correct operation. I/O Access Enable. The Coral-PA does not do I/O Accesses. Description MB86296S 152 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL PCI Status Register Bit 15 14 13 12 11 10-9 8 7 6 5 4-0 Type Status Status Status Status Status RO Status RO RO - 0 0 0 0 Reset Value 0 01 0 1 0 0 - Parity Error has been detected by the Coral-PA. System Error has been signaled by the Coral-PA. Received Master Abort. Set to `1' when a PCI Master terminates a user to the Coral-PA transaction with Master Abort. Received Target Abort. Set to `1' when the Coral-PA has initiated a transaction that has been terminated by Target Abort. Target Abort has been signaled by the Coral-PA. Device Select Timing. Indicates the timing of the DEVSEL# signal when the Coral-PA responds as a PCI Target. Data Parity Error detected. Fast Back-to-Back Capable Status Flag. Reserved 66MHz Capable Flag. Reserved Description Revision ID Register Bit 7-0 Type ER Reset Value 01h Description Revision ID of the Coral-PA. PCI Class Code Register Bit 23-0 Type ER Reset Value 038000h Class Code of the Coral-PA. The Reset value means "Display Controller" of non-specific type. Description Casheline Size Register Bit 7-0 Type RW Reset Value 0 Description Casheline Size. Master Latency Timer Register Bit 7-2 Type RW Reset Value 0 1-0 - 0 Master Latency Timer Count Value. This register sets the minimum number of PCI clocks the Coral-PA is guaranteed access to the PCI bus. After the count has expired, the Coral-PA releases the PCI bus as soon as another PCI Master is granted the bus by the bus arbiter. Reserved Description Header Type Register Bit 7-0 Type ER 0 Reset Value Description As defined in the PCI Specification, Section 6.2.1. BIST Register Bit 7-0 - Type Reset Value 0 Description This field is not used by the Coral-PA, so it is hard-wired to zero. MB86296S 153 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Memory Base Address Register Bit 31 RW Type Reset Value 0 Memory Base Address. This determines the address of the first Coral-PA non PCI register. The Coral-PA will respond as a Target to accesses in the address range: (memory_base_address) to (memory_base_address + 3FF0000H) Description Subsystem Vendor ID Register Bit 15-0 Type ER 0 Reset Value Description Subsystem Vendor ID. This register can be loaded from EEPROM. Subsystem ID Register Bit 15-0 Type ER 0 Reset Value Description Subsystem ID. This register can be loaded from EEPROM Interrupt Line Register Bit 7-0 Type RW Reset Value 0 Description Interrupt Line Register. Used to convey interrupt line routing information. Interrupt Pin Register Bit 7-0 Type RW Reset Value 1 Description Identifies which PCI Interrupt pin the Coral-PA is connected to. The default value of this indicate that the Coral-PA is connected to the INTA line, which is the usual setting for this field. Min Grant Register Bit 7-0 Type ER 0 Reset Value Description Identifies the maximum length of PCI burst period the Coral-PA needs. This should be left at the reset setting. Max Latency Register Bit 7-0 Type ER 0 Reset Value Description Specifies how often the Coral-PA needs to access the bus. This should be left at the reset settings. TRDY Timeout Value Register Bit 7-0 Type RW Reset Value 80h Description Sets the number of PCI clocks the Coral-PA will wait for TRDY, when acting as a Bus Master. Retry Timeout Value Register Bit 7-0 Type RW Reset Value 80h Description Sets the number of retries of the Coral-PA will perform when acting as a Bus Master. User Programmable Register Bit 31-0 Type ER MB86296S 0 Reset Value Description User programmable register 154 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13 Local Memory Registers 13.1 Local memory register list 13.1.1 Host interface register list Base = HostBase Offset 0020 0024 002C 0038 005C 00A0 00A4 FRST SRBS SRBS FRST CCF CGE COT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7654321 0 IST IST IMASK IST IMASK IMASK IMASK SRST SRST RSW RSW I IST MB86296S 155 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 00A8 00AC 00B0 00B4 00B8 00F0 8000 8004 STRT NDA NSA IOM GIM GD GWE SIC CK D SID FSL FS TLS RWD TRC NP CID CN BSA SA BDA DA BCR BSIZE BSR XCOR IMODE TCM BCM EXTEN BER ABORT EXTST BEN TCNT BCB RWDATA * 8 BST TC BC MODE TSIZE VER CKP CKG DOE SD SP SL GD GD SER RGB BEE SBE TCE BCE EEE 8008 800C 8010 8014 8040 ... 805C MB86296S 156 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.1.2 I2C interface register list Base = I2CBase Offset 000 004 008 00C 010 014 018 01C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Access Prohibitation Access Prohibitation Access Prohibitation BSR BCR CCR ADR DAR 13.1.3 Graphics memory interface register list Base = HostBase Offset FFFC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTC LOWD TRRD TRCD TWR SAW TRC TRAS RTS ASW TRP CL ID MB86296S 157 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.1.4 Display controller register list Offset 000 Base = DisplayBase 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 DCE (Display Controller Enable) L45E L23E L1E L0E CKS DCS DEN DCM (Display Control Mode) SC SYNC L0WP SYNC EEQ EDE EOF EOD SF ESY CKinv CKDe DCEE (Display Controller Extend Enable) SC EEQ EDE EOF EOD SF ESY CKDn DEN L5E L4E L3E L2E L1E L0E CKS DCS DCM2 (Display Control Mode 2) DCM3 (Display Control Mode 3) RUF RUM 100 104 108 004 008 00C 010 014 018 01C L0C VSWH HTP (H Total Pixels) HDB (H Display Boundary) VSW HSW VTR (V Total Rasters) VDP (V Display Period) WY (Window Y) WH (Window Height) HDP (H Display Period) HSP (H Sync pulse Position) VSP (V Sync pulse Position) WX (Window X) WW (Window Width) 020 024 028 02C L0EC 110 114 118 L0M (L0 Mode) L0S (L0 Stride) L0H (L0 Height) L0OA (L0 Origin Address) L0DA (L0 Display Address) L0DY (L0 Display Y) L0DX (L0 Display X) L0EM (L0 Extend Mode) L0PB L1C L1YC L1CS L1IM 030 034 L0WY (L0 Window Y) L0WH (L0 Window Height) L1M (L1 Mode) L1S (L1 Stride) L0WX (L0 Window X) L0WW (L0 Window Width) L1DA (L1 Display Address) L1EM (L1 Extend Mode) L1EC 120 DM L1PB MB86296S 158 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L2M (L2 Mode) L2FLP L2C 040 044 048 04C 050 054 L2S (L2 Stride) L2H (L2 Height) L2OA0 (L2 Origin Address 0) L2DA0 (L2 Display Address 0) L2OA1 (L2 Origin Address 1) L2DA1 (L2 Display Address 1) L2DY (L2 Display Y) L2DX (L2 Display X) L2EM (L2 Extend Mode) L2PB L2OM L2WP L2EC 130 134 138 L2WY (L2 Window Y) L2WH (L2 Window Height) L2WX (L2 Window X) L2WW (L2 Window Width) MB86296S 159 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 058 05C 060 064 068 06C L3EC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L3M (L3 Mode) L3FLP L3S (L3 Stride) L3H (L3 Height) L3C L3PB 144 148 L4C 070 074 078 07C 080 084 L4FLP L3WY (L3 Window Y) L3WX (L3 Window X) L3WH (L3 Window Height) L3WW (L3 Window Width) L4M (L4 Mode) L4S (L4 Stride) L4H (L4 Height) L4OA0 (L4 Origin Address 0) L4DA0 (L4 Display Address 0) L4OA1 (L4 Origin Address 1) L4DA1 (L4 Display Address 1) L4DY (L4 Display Y) L4DX (L4 Display X) L4EM (L4 Extend Mode) L4OM L4WP 154 158 L5FLP L5C L4EC 150 L4WY (L4 Window Y) L4WH (L4 Window Height) L5M (L5 Mode) L5S (L5 Stride) L4WX (L4 Window X) L4WW (L4 Window Width) L5H (L5 Height) 088 08C 090 094 098 09C 164 168 L5WY (L5 Window Y) L5WH (L5 Window Height) L5WX (L5 Window X) L5WW (L5 Window Width) MB86296S 160 L5OM L5WP L5EC 110 L5OA0 (L5 Origin Address 0) L5DA0 (L5 Display Address 0) L5OA1 (L5 Origin Address 1) L5DA1 (L5 Display Address 1) L5DY (L5 Display Y) L5X (L5 Display X) L5EM (L5 Extend Mode) L3OM L3WP 140 L3OA0 (L3 Origin Address 0) L3DA0 (L3 Display Address 0) L3OA1 (L3 Origin Address 1) L3DA1 (L3 Display Address 1) L3DY (L3 Display Y) L3DX (L3 Display X) L3EM (L3 Extend Mode) FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL MB86296S 161 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 0A0 0A4 0A8 0AC 0B0 180 184 0B4 188 18C 190 194 198 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSIZE CSIZ1 CSIZ0 CPM CUO1 CUO0 CUE1 CUE0 CUTC (Cursor Transparent Control) CUZT CUTC CUOA0 (CUrsor0 Origin Address) CUY0 (Cursor0 Position Y) CUX0 (Cursor0 Position X) CUOA1 (CUrsor1 Origin Address) CUY1 (Cursor1 Position Y) CUX1 (Cursor1 Position X) DLS (Display Layer Select) DLS5 DLS4 DLS3 DLS2 DLS1 DLS0 DBGC (Display Back Ground Color) L0BLD (L0 Blend) L0BE L0BS L0BI L0BP L0BR L1BR L2BR L3BR L4BR L5BR L1BLD (L1 Blend) L2BLD (L2 Blend) L3BLD (L3 Blend) L4BLD (L4 Blend) L5BLD (L5 Blend) L5BE L5BS L5BI L4BE L4BS L4BI L4BP L3BE L3BS L3BI L3BP L2BE L2BS L2BI L2BP L1BE L1BS L1BI L1BP MB86296S 162 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 0BC L2ZT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L0TC (L0 Transparent Control) L0ZT L0TC (L0 Transparent Color) L3TR (L3 Transparent Control) L3TR (L3 Transparent Color) L2TC (L2 Transparent Color) L0EZT 1A0 1A4 1A8 1AC 1B0 1B4 1E0 1E4 1E8 1EC 1F0 1F4 L0TEC (L0 Extend Transparency Control) L0ETC (L0 Extend Transparent Color) L1TEC (L1 Transparent Extend Control) L1EZT L1ETC (L1 Extend Transparent Color) L2TEC (L2 Transparent Extend Control) L2EZT L2ETC (L2 Extend Transparent Color) L3TEC (L3 Transparent Extend Control) L3EZT L3ETC (L3 Extend Transparent Color) L4ETC (L4 Extend Transparent Control) L4EZT L4ETC (L4 Extend Transparent Color) L5ETC (L5 Extend Transparent Control) L5EZT L5ETC (L5 Extend Transparent Color) L1YCR0 (L1 YC to Red Coefficient 0) a12 L1YCR1 (L1 YC to Red Coefficient 1) b1 L1YCG0 (L1 YC to Green Coefficient 0) a22 L1YCG1 (L1 YC to Green Coefficient 1) b2 L1YCB0 (L1 YC to Blue Coefficient 0) a32 L1YCB0 (L1 YC to Blue Coefficient 0) b3 L3ZT 0C0 L2TR (L2 Transparent Control) a11 a13 a21 a23 a31 a33 MB86296S 163 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 400 404 : 7FC 800 804 : BFC 1000 1004 : 13FC 1400 1404 : 17FC A R L3PAL1 : L3PAL255 A R L2PAL1 : L2PAL255 L3PAL0 G B A R L1PAL1 : L1PAL255 L2PAL0 G B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L0PAL0 A R L0PAL1 : L0PAL255 L1PAL0 G B G B MB86296S 164 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.1.5 Video capture register list Base = CaptureBase Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VIE CM 004 008 00C VSCI CSC (Capture SCale) VSCF HSCI VCS (Video Capture Status) VCS_MSK (Video Capture Status MASK) HSCF CE MSK_CE SSM CBST HP VP HRV OOM SBUF CRGB PAU CBW (stride) C24 BED CSW 010 014 018 01C 020 028 040 048 04C 080 084 088 CBM (Capture Buffer Mode) SSS CIVSTR CIVEND CBOA (Capture Buffer Origin Address) CBLA (Capture Buffer Limit Address) CHP (Capture Horizontal Pixel) CIHSTR CIHEND CHP CLPF (Capture Low Pass Filter) CVLPF CHLPF CMSS (Capture Magnify Source Size) CMSHP CMSVL CMDS (Capture Magnify Display Size) CMDHP CMDVL RGBHC(RGB input HSYNC Cycle)/VIN_HSSIZE RGBHEN(RGB input Horizontal Enable Area) RGBHST RGBHEN RGBVEN(RGB input Vertical Enable Area) RGBVST RGBVEN RGBS(RGB input SYNC) RGBCMY(RGB Color convert Matrix Y coefficient) a12 RGBCMCb(RGB Color convert Matrix Cb coefficient) a22 RGBCMCr(RGB Color convert Matrix Cr coefficient) a32 RM RGBHC 090 0C0 0C4 0C8 a11 a21 a31 a13 a23 a33 MB86296S 165 NRGB VS VICE VIS VI 000 VCM (Video Capture Mode) FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 0CC b1 RGBCMb(RGB Color convert Matrix b coefficient) b2 b3 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 4000 4004 CDCN(Capture Data Count for NTSC) BDCN CDCP(Capture Data Count for PAL) BDCP 9 8 7 6 5 4 3 2 1 0 VDCN VDCP 9 8 7 6 5 4 3 2 1 0 Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MB86296S 166 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.1.6 Drawing engine register list The parenthesized value in the Offset field denotes the absolute address used by the SetRegister command. Base = DrawBase Offset 000 (000) 004 (001) 008 (002) 00C (003) 010 (004) 014 (005) 018 (006) 01C (007) 020 (008) 040 (010) 044 (011) 048 (012) 04C (013) 050 (014) 054 (015) 058 (016) 05C (017) 060 (018) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSSS SSSS SSSS SSSS SSSS SSSS SSSS 0000 0000 00000000 SSSSSSSS SSSSSSSS 00000000 SSSSSSSS SSSSSSSS 00000000 SSSSSSSS SSSSSSSS Int Int Int Int Int Int Int Int Int Int Int Int Int Int Int Int Int Int Ys Xs Frac Frac Frac Frac Frac Frac Frac 0 0 Frac Frac Frac Frac Frac Frac Frac Frac Frac dXdy XUs dXUdy XLs dXLdy USN LSN Rs dRdx dRdy Gs dGdx dGdy Bs dBdx dBdy MB86296S 167 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 080 (020) 0 084 (021) S 088 (022) S 0C0 (030) S S S 0C4 (031) S S S 0C8 (032) S S S 0CC (033) S S S 0D0 (034) S S S 0D4 (035) S S S 0D8 (036) 0 0 0 0 0 0 0 0DC (037) S S S S S S S 0E0 (038) S S S S S S S 140 (050) 0 0 0 0 144 (051) S S S S INT Zs Int dZdx Int dZdy Int Ss Int dSdx Int dSdy Int Ts Int dTdx Int dTdy Int Qs Frac dQdx INT Frac dQdx INT Frac LPN Int LXs Int Int Frac Frac Frac Frac Frac LZde Int Frac Int 0 Frac Frac Frac Frac Frac Frac Frac Frac Frac LXde 148 (052) S S S S S S S S S S S S S S S 14C (053) S S S S LYs Int LYde 150 (054) S S S S S S S S S S S S S S S 154 (055) S 158 (056) S LZs Int MB86296S 168 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 180 (060) 184 (061) 188 (062) 200 (080) 204 (081) 208 (082) 20C (083) 240 (090) 244 (091) 248 (092) 24C (093) 250 (094) 254 (095) 258 (096) 25C (097) 250 (098) 254 (099) 258 (09A) 3E0 (0f8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PXdc SSSS SSSS S SSSS SSSS SSSS SSSS 0000000 SStride 0000 0000 0000 0000000 Int PYdc Frac Frac PZdc Frac RXs Int Int Int RYs 0 0 RsizeX 0 RsizeY 0 SADDR Address Int Int Int Int SRXs 0 0 SRYs 0 DADDR Address DStride Int Int 0000 0000 0000 0000 0000 Int DRXs 0 0 DRYs 0 BRsizeX 0 BRsizeY 0 TColor Color BLPO BCR Int Int Int Int 0 MB86296S 169 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 400 (100) 404 (-) 408 (-) 40C (-) 410 (-) 414 (-) 418 (-) 420 (108) 424 (109) 428 (10a) 42C (10b) 430 (10c) 43C (10f) TT MDR3 TWS TWT TAB TBL MDR4 LOG MDR7 PGH PTH PZH LTH EZ GG BM TE TBU BA TC TF ZP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTR FCNT IFSR IFCNT FCNT SST SS DS DS PST PS EST MDR0 CF BSV BSH CY CX FD PE CE MDR1/MDR1S/MDR1B/MDR1TL FD FE CE SS DS PS FD FE CE NF FF FE LOG LOG LW BM BM ZCL ZCL ZW MDR2/MDR2S/MDR2TL ZW ZC AS SM MB86296S 170 ZC AS SM BP BL FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 440 (110) 444 (111) 448 (112) 44C (113) 450 (114) 454 (115) 458 (116) 45C (117) 460 (118) 464 (119) 468 (11a) 46C (11b) 470 (11C) 474 (11D) 480 (120) 484 (121) 488 (122) 48C (123) 494 (129) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FBR FBASE XRES XRES ZBR ZBASE TBR TBASE PFBR PFBASE CXMIN CLIPXMIN CXMAX CLIPXMAX CYMIN CLIPYMIN CYMAX CLIPYMAX TXS TXSN TIS TISN TOA XBO SHO SHOFFS ABR ABASE FC FGC8/16/24 BC BGC8/16/24 ALF A BLP TBC BC16/24 TISM TXSM MB86296S 171 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Offset 540 (150) 544 (151) 548 (150) 54C (151) 580 (160) 584 (161) 588 (162) 58C (163) 590 (164) 594 (165) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LX0dc 0000 Int LY0dc Int LX1dc Int LY1dc Int X0dc Int Y0dc Int X1dc Int Y1dc Int X2dc Int Y2dc Int 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 MB86296S 172 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.1.7 Geometry engine register list The parenthesized value in the Offset field denotes the absolute address used by the SetRegister command. Base = GeometryBase Offset 000 (-) 040 (2010) 044 (2011) PO TC LV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GCTR FCMT GS DF BO CF SS ST Z EP EP FD FD PS C F CF CF AA AA FO NF UW GMDR0 GMDR1 GMDR1E BM TM 048 (2012) - GMDR2 GMDR2E DFIFOG SP TL 400 (-) MB86296S 173 BO BC BP SP - FE FF FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.2 Explanation of Local Memory Registers Terms appeared in this chapter are explained below: 1. Register address Indicates address of register 2. Bit number Indicates bit number 3. Bit field name Indicates name of each bit field included in register 4. R/W Indicates access attribute (read/write) of each field Each symbol shown in this section denotes the following: R0 W0 R W RX RW RW0 "0" always read at read. Write access is Don't care. Only "0" can be written. Read enabled Write enabled Read enabled (read values undefined) Read and write enabled Read and write 0 enabled 5. Initial value Indicates initial value of immediately before the reset of each bit field. 6. Handling of reserved bits "0" is recommended for the write value so that compatibility can be maintained with future products. MB86296S 174 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.2.1 Host interface registers IST (Interrupt STatus) Register HostBaseAddress + 20H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name IST *1 Reserved Resv Reserved Resv IST IST R/W RW0 R RW0 R0 R0W0 R0 R0 RW0 RW0 *1 Reserved This register indicates the current interrupt status. It shows that an interrupt request is issued when "1" is set to this register. The interrupt status is cleared by writing "0" to this register. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 17 and 16 CERR (Command Error Flag) Indicates drawing command execution error interrupt CEND (Command END) Indicates drawing command end interrupt VSYNC (Vertical Sync.) Indicates vertical interrupt synchronization FSYNC (Frame Sync.) Indicates frame synchronization interrupt SYNCERR (Sync. Error) Indicates external synchronization error interrupt REGUD (Register update) Indicates register update interrupt Reserved This field is provided for testing. Normally, the read value is "0", but note that it may be "1" when a drawing command error (Bit 0) has occurred. SII (Serial Interface Interrupt) Indicates a serial interface write/read has completed. GI (GPIO Interrupt) Indicates that a GPIO input has changed state (0->1 or 1->0) BC (Burst Complete) Indicates that a burst has completed (as part of a Burst Control Unit transfer). Note that this bit is cleared by writing to the BST (Burst Status) register, not the IST. TC (Transfer Complete) Indicates that a transfer is complete (as controlled by the Burst Control Unit). Note that this bit is cleared by writing to the BST (Burst Status) register, not the IST. HF (HIF Fatal) Indicates that a fatal error occurred in a PCI transfer. AE (Address Error) Indicates that an invalid address was specified for an access (eg. Host Interface registers as a BCU source address). Initial value 0 0 0 R0 0 0 0 0 0 0 0 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 MB86296S 175 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL IMASK (Interrupt MASK) Register HostBaseAddress + 24H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserve IMASK IMASK IMASK *1 Reserved Resv Reserved d RW 0 R0 0 R0 0 R0W0 R/W Initial value R0 0 RW 0 RW 0 0 *1 Reserved This register masks interrupt requests. Even when the interrupt request is issued for the bit to which "0" is written, interrupt signal is not asserted for CPU. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 CERRM (Command Error Interrupt Mask) Masks drawing command execution error interrupt CENDM (Command Interrupt Mask) Masks drawing command end interrupt VSYNCM (Vertical Sync. Interrupt Mask) Masks vertical synchronization interrupt FSYNCH (Frame Sync. Interrupt Mask) Masks frame synchronization interrupt SYNCERRM (Sync Error Mask) Masks external synchronization error interrupt REGUD (Register update) Masks register update interrupt SIIM (Serial Interface Interrupt) Masks serial interface interrupt. GIM (GPIO Interrupt) Masks GPIO interrupt. BCM (Burst Complete) Masks Burst Complete interrupt. TCM (Transfer Complete) Masks Transfer complete interrupt. HFM (HIF Fatal) Masks HIF fatal interrupt. AEM (Address Error) Masks address error interrupt. MB86296S 176 R0 0 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL SRST (Software ReSeT) Register HostBaseAddress + 2CH address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 SRST W1 0 This register controls software reset. When "1" is set to this register, a software reset is performed. CCF (Change of Clock Frequency) This register changes the operating frequency. Bit 19 and 18 Register HostBaseAddress + 0038 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CGE COT Reserved R/W RW0 RW RW RW0 Initial value 0 00 00 0 CGE (Clock select for Geometry Engine) Selects the clock for the geometry engine 11 Reserved 10 166 MHz 01 133 MHz 00 100 MHz COT (Clock select for the others except-geometry engine) Selects the clock for other than the geometry engine 11 Reserved 10 Reserved 01 133 MHz 00 100 MHz Bit 17 and 16 Notes: 1. Write "0" to the bit field other than the above ([31:20], [15:00]). 2. Operation is not assured when the clock setting relationship is CGE < COT. MB86296S 177 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL RSW (Register location Switch) Setting this register will move the register area from the center (1FC0000) to the end of the CORAL area (3FC0000). This move can be performed when "1" is written to this register. Set this register at the first access after reset. Access CORAL after about 20 bus clocks after setting the register. Register HostBaseAddress + 5C H address Bit number 7 6 5 Bit field name R/W Initial value 4 Reserved R0 0 3 2 1 0 RSW RW 0 FRST (Firm ReSeT) Reserved R0 0 Initial value Writing a "1b" to this register will trigger a Firm Reset. This resets the complete device (as far as possible) including the PCI Interface. MB86296S 178 RW 0 R/W FRST Register HostBaseAddress + 00A0H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL SRBS (Slave Read Burst Size) Register HostBaseAddress + 00A4H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved SRBS R/W R0 RW Initial value 0 0 This register specifies the length of a burst read through the PCI Slave Interface as SRBS+1. By default this register is set to "000b" indicating a burst read length of 1 dword. The maximum setting is 7 ("111b") and indicates a burst read length of 8 dwords. IOM (IO Mode) Resv. R0 0 GIM RW 0 GD Initial value 0 *1 - initial reset value specified by Burst Enable pin state at reset. *2 - initial reset value specified by Transfer Complete pin state at reset. This register determines the function of those Coral PA pins under the control of the host interface. It also defines the direction (input/output) of any GPIO. Bit 0 EEE (EEPROM Enable) If set then the PCI EEPROM Configuration function is enabled. This field takes it's reset value from the Transfer Complete pin at system reset. Note that if the RGB input is enabled then the EEPROM interface us disabled regardless of the value of this register. If this field is "0b" (and the RGB input is not enabled) then the EEPROM pins operate either as serial interface pins or GPIO as determined by the SER field. BCE (Burst Complete Enable) If set to "1b" then the BC pin operates as Burst Complete. Otherwise if set to "0b" it operates as a GPIO. If the RGB input is enabled this field is ignored and the BC pin operates as an RGB input pin. TCE (Transfer Complete Enable) If set to "1b" then the TC pin operates as Transfer Complete. Otherwise if set to "0b" it operates as GPIO. SBE (Slave Busy Enable) If set to "1b" then the SB pin operates as Slave Busy. Otherwise if set to "0b" it operates as a GPIO. If the RGB input is enabled this field is ignored and the SB pin operates as an RGB input pin. BEE (Burst Enable Enable) If set to "1b" then the BEN pin operates as Burst Enable. Otherwise if set to "0b" it operates as GPIO. RGB (RGB input enable) If set to "1b" then the RGB input is enabled. This field takes its reset value from the Burst Enable pin at system reset and overrides all other IO enable fields. Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 MB86296S 179 RW RW RW RW RW RW RW 0 *1 0 0 0 0 *2 R/W RW SER RGB BEE SBE TCE BCE EEE Register HostBaseAddress + 00A8H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Bit 6 SER (SERial Interface enable) If set to "1b" then the serial interface is enabled. This field is ignored if either the RGB input or EEPROM is enabled. For the serial interface strobe signal to be used the SBE field must also be clear ("0b"). GD (GPIO Direction) Specifies the direction of pins acting as GPIO. If a bit is "0b" then the pin acts as an input. Otherwise if set to "1b" it operates as an output. The mapping to pins is: Bit 7: EDO Bit 8: EDI Bit 9: ECK Bit 10: ECS Bit 11: EE Bit 12: BC Bit 13: TC Bit 14: SB Bit 15: BEN GIM (GPIO Interrupt Mask) Masks (enables) interrupt triggering on a GPIO pin by pin basis. If a bit is set to "1b" then a change in stage of that pin (0->1 or 1->0) can trigger an interrupt via the IST register. Otherwise if set to "0b" no interrupt will be triggered. Care should be taken to disable interrupts on pins not operating as GPIO inputs, otherwise unwanted interrupts may occur. The mapping to pins is: Bit 16: EDO Bit 17: EDI Bit 18: ECK Bit 19: ECS Bit 20: EE Bit 21: BC Bit 22: TC Bit 23: SB Bit 24: BEN Bit 25: GI0 Bit 26: GI1 Bit 27: GI2 Bit 28: GI3 Bit 29: GI4 Bit 15 to Bit 7 Bit 29 to Bit 16 MB86296S 180 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL GD (GPIO Data) Register HostBaseAddress + 00ACH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved GWE Resv GD R/W R0 W R0 RW Initial value 0 0 0 0 (*1) *1 - initial value will be affected by state of GPIO pins This register contains the GPIO read/write data field and the write mask when setting GPIO outputs. Bit 13 to Bit 0 GD (GPIO Data) This field is used for both reading the value of GPIO inputs and specifying the value for GPIO outputs. When writing to this field only those pins with the corresponding bit set in the GWE field will be changed. The bit positions refer to the following pins: Bit 0: EDO Bit 1: EDI Bit 2: ECK Bit 3: ECS Bit 4: EE Bit 5: BC Bit 6: TC Bit 7: SB Bit 8: BEN Bit 9: GI0 Bit 10: GI1 Bit 11: GI2 Bit 12: GI3 Bit 13: GI4 GWE (GPIO Write Enable) When writing values to the GPIO Outputs using the GD field, this field specifies those bits which are being written to. If a bit in this field is "1b" then the corresponding bit will be written to. Otherwise if a bit it "0b" the corresponding bit will remain unchanged. The bit positions refer to the following pins: Bit 16: EDO Bit 17 EDI Bit 18: ECK Bit 19: ECS Bit 20: EE Bit 21: BC Bit 22: TC Bit 23: SB Bit 24: BEN Bit 24 to Bit 16 MB86296S 181 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL SIC (Serial Interface Control) Register HostBaseAddress + 00B0H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CKP CKG Reserved R0 0 CKD RW 0 Reserved R0 0 DOE Reserved R0 0 RW RW RW This register provides control for the serial interface protocol and clock. Bit 0 SL (Strobe Length) If set to "0b" then the strobe signal is only active for one cycle at the start of a transfer. Otherwise if set to "1b" it is active for the duration of the cycle. Note that this field may be overridden for a single transaction using the FS/FSL fields in the SID register. SP (Strobe Polarity) If set to "0b" then strobe is active low. Otherwise if set to "1b" it is active high. SD (Strobe Disable) If set to "1b" then the serial interface strobe is disabled. Note that this field may be overridden foe a single transaction using the FS field in the SID register. DOE (Data Output Enable control) If set to "0b" then the Data Out signal is driven permanently even when transactions are not in progress. If set to "1b" then the Data Out is driven only during active cycles. CKD (Clock Divisor) This field specifies the serial interface clock divisor. The main system clock is divided down by one of the following factors: 00b: 16 01b: 32 10b: 64 11b: 128 Based on a 133MHz internal clock these yield frequencies of approximately 8.3MHz, 4.1MHz, 2.0 MHz and 1.0MHz respectively. CKG (Clock Gating) When set to "1b" the serial interface clock is only active during active transfers. Otherwise if set to "0b" it is active continuously. Note that the CKP field specifies the inactive value when the clock is static. CKP (Clock Polarity) When set to "0b" data/strobe are clocked out on a falling edge of the serial interface clock and data in is clocked in on the next falling edge. When clock gating is enabled (by setting the CKG field) the static level is low. When set to "1b" data/strobe are clocked out on a rising edge of the serial interface clock and data in is clocked in on the next falling edge. When clock gating is enabled (by setting the CKG field) the static level is high. Initial value 00 0 Bit 1 Bit 2 Bit 8 Bit 17 to Bit 16 Bit 18 Bit 19 MB86296S 182 RW RW RW 000 R/W SD SP SL FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL SID (Serial Interface Data) Register HostBaseAddress + 00B4H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved R0 0 FSL FS TLS RW 0 RWD RW 0 RW RW 00 R/W Initial value This register is used to write/read serial interface data, enable a transfer and monitor a transfers progress. Bit 0 to Bit 7 RWD (Read/Write Data) When written to specifies the serial output data. When read it contains the serial interface input data. Note that data will be shifted out top bit (bit 7) first down to the bottom bit (bit 0) last. Read data will be shifted in to the bottom bit and shifted up by by each bit of the transfer. For transfer of length 8 this will yield consistent read/write data. For transfers of less than 8 bits then identical read and write data will appear different. TLS (Transfer Length/Status) Specifies the length of a transfer and can be used to monitor its status. For each bit of a transfer this field is shifted up by one until it is "00000000b". For example, to specify a transfer of 8 bits "00000001b" should be written. To specify a transfer of 3 bits "00100000" should be written. FS (Force Strobe) For a single transfer this field can be used to override settings in the SIC register. If set to "1b" then a strobe will be done with a length specified in the FSL field. FSL (Force Strobe Length) For a single transfer if the FS field is set this field overrides the SL field in the SIC register and specifies the Strobe Length for the transfer. A value of "0b" specifies a strobe only for the first active cycle of the transfer. A value of "1b" specifies a strobe active for the whole transfer. Bit 15 to Bit 8 Bit 16 Bit 17 MB86296S 183 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL TRC (Transfer Rate Change) Register HostBaseAddress + B8H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved R0W0 *1 Initial value 0 *1 Reserved ON/OFF of the pre-fetch function at the time of slave read is changed. Please set 0x00000002 at the hardware initialization, for turning OFF a pre-fetch function. Except for the hardware initialization, when you change a setup of this bit into 1 from 0, please perform the following procedure. After slave burst READ to the last graphic memory, Write 0x00000000 to the domain which is not using a graphics memory. And read Host interface register (ex. HostBase+BFFC) Then, set this bit to 1. when you change a setup of this bit into 0 from 1, there is especially no restriction. Bit 1 NP (No pre-fetch mode ) 0: pre-fetch function ON 1: pre-fetch function OFF MB86296S 184 RW R0W0 00 R/W NP FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL CID (Chip ID register) Register HostBaseAddress + 00f0 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CN VER R/W R0 R R Initial value 0 0000_0011 0000_1000 This is the chip identification register. Bit 7 to 0 VER (VERsion) This field indicates the chip's unique version number. Note that the unique version number for the ES version and that of the mass-produced version are different. 0000_0000 ES 0000_0001 Reserved 0000_0010 Reserved for CoralQ 0000_0011 Reserved for Coral B 0000_0100 Reserved 0000_0101 Reserved 0000_0110 Reserved for P (Coral P value) others Reserved 0000_1000 Reserved for PA (Coral PA value) CN (Chip Name) This field indicates the chip name. 0000_0000 Reserved 0000_0001 Reserved 0000_0010 Reserved 0000_0011 CORAL others Reserved Bit 15 to 8 MB86296S 185 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL BSA (Burst Source Address) Register HostBaseAddress + 8000 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name SA R/W RW Initial value 0 This register specifies the initial source address for a transfer controlled by the Burst Control Unit. Its interpretation (internal Coral/external PCI) will depend on the transfer mode specified in the BSR register. BDA (Burst Destination Address) This register specifies the initial destination address for a transfer controlled by the Burst Control Unit. Its interpretation (internal Coral/external PCI) will depend on the transfer mode specified in the BSR register. Register HostBaseAddress + 8004 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DA R/W RW Initial value 0 BCR (Burst Control Register) RW STRT RW NDA RW NSA R0 Register HostBaseAddress + 8008 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name *1 BSIZE TSIZE R/W RW 0 RW 0 *1 - Reserved This register specifies the length and address manipulation performed for a transfer. It can also be used to start a transfer. TSIZE This field specifies the overall transfer length as a number of dwords. A transfer will be split up into a number of bursts whose length is specified by the BSIZE field. Bit 27 to 24 BSIZE (Burst Size) This field specifies the length of a BCU controlled burst as a number of dwords. One or more bursts will make up an overall transfer. Note that if TSIZE is not an exact multiple of BSIZE the final burst of a transfer will be less than BSIZE. Bit 29 NSA (New Source Address) If this bit is set to "1b" then after each burst the source address is incremented by the burst size. This means that a large continuous section of memory can be transferred. If this bit is "0b" then successive bursts will always be from the initial specified start address. This mode could be used if transferring data from a FIFO like interface. Bit 30 NDA (New Destination Address) If this bit is set to "1b" then after each burst the destination address is incremented by the burst size. This means that data can be transferred into a large continuous section of memory. If this bit is "0b" then successive bursts will always be to the initial specified destination address. This mode should be used when transferring data to the FIFO. Bit 23 to 0 Initial value 0 0 0 0 MB86296S 186 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Bit 31 STRT (STaRT transfer) When set to "1b" a transfer is started. Otherwise the transfer will wait until triggered wither through the Burst Enable Register (BER) or via the external burst enable signal. BSR (Burst Setup Register) Reserved XCOR IMODE TCM BCM EXTEN RW RW RW RW RW 00000 Register HostBaseAddress + 800C H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name MODE RW 0 R/W Initial value R0 0 This register specifies the type of a transfer (interpretation of the addresses) and specifies the setup of control signals/status bits. Bit 2 to 0 MODE (transfer MODE) This field specifies the mode of the transfer and thus the interpretation of the source/destination addresses. 000b: Slave Mode PCI to Coral 001b: Slave Mode Coral to PCI 010b: Coral to Coral (internal transfer) 011b: Reserved 100b: PCI to Coral (PCI Master read) 101b: Coral to PCI (PCI Master write) 110b: PCI to PCI (PCI Master read/write external DMA transfer) 111b: Reserved Refer to Chapter 3 for a detailed explanation of these modes. EXTEN (EXTernal ENable) If set to "1b" then the external BEN (Burst Enable) signal may be used to initiate and pause a transfer. Otherwise if set to "0b" the external BEN signal is ignored. BCM (Burst Complete Mask) If set to "1b" then the external BC signal will be active. Otherwise if set to "0b" it will remain inactive low. Note that this bit does not affect the Burst Complete indication in the main interrupt status register (IST) or the triggering of the main external interrupt. TCM (Transfer Complete Mask) If set to "1b" then the external TC signal will be active. Otherwise if set to "0b" it will remain inactive low. Note that this bit does not affect the Transfer Complete indication in the main interrupt status register (IST) or the triggering of the main external interrupt. IMODE (Interrupt Mode) This bit controls how the external BC/TC signals operate. If set to "0b" they are active high. Otherwise if set to "1b" they toggle at each change of state removing the need for the host to read/write the status register to clear them down. Note that when using the Burst Complete/Transfer Complete indications via the main interrupt status register this field should always be "0b". XCOR (not Clear On Read) If set to "0b" then the Burst Complete/Transfer Complete fields in the Burst Status register are clear on read. Otherwise if set to "1b" they must be manually written. Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 MB86296S 187 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL BER (Burst Enable Register) Register HostBaseAddress + 8010 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ABORT Reserved R0 0 *1 Reserved RX Don't Care Reserved R0 0 R0 Initial value 00 00 *1 - Reserved This register can be used to enable/pause/abort a transfer. It can also be used to monitor the state of the external Burst Enable signal. Bit 0 BEN (Burst ENable) When set to "1b" a transfer is enabled. This bit will also become set if the STRT bit in the BCR register is set. During a transfer this may be cleared to "0b" to pause/halt a transfer at the next boundary between bursts. Setting it back to "1b" will re-enable the transfer from the position it had reached. EXTST (External Status) Provided the state of the external Burst Enable signal. ABORT Under some circumstances clearing the BEN field may not halt a transfer. This will happen if the Burst Controller is waiting for an external PCI Master to take some action. In this case writing "1b" to the ABORT field will cancel the transfer. The transfer will not be able to be re-started. Bit 1 Bit 16 BST (Burst STatus) Register HostBaseAddress + 8014 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved TCNT R/W RR Initial value 0 0 TC BC R0 0 R 0 This register is used to monitor the state of the current transfer. Bit 23 to 0 Bit 30 Bit 31 TCNT (Transfer CouNT) Gives the current transfer count as a number of dwords remaining to be transferred. BC (Burst Complete) Indicates the state of a burst. Note that when in active high mode this field will remain high following a burst unless it is cleared either by a clear on read or by writing 0 to it. TC (Transfer Complete) Indicates the state of the current transfer. When set to "1b" the transfer is complete. MB86296S 188 RW R/W W EXTST BEN R FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL BCB (Burst Controller Buffer) Register HostBaseAddress + 8040 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name RWDATA * 8 R/W RW Initial value 0 This buffer is used by the Burst Controller as a temporary store while executing transfers. The user should only need to access it when using modes "000b" and "001b" - the PCI slave modes. These can be used to transfer large quantities of data to/from the Coral PA in PCI Slave mode with automatic pre-fetch/write of data with address incrementing. MB86296S 189 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.2.2 I2C Interface Registers BSR (Bus Status Register) Register address Bit No Bit field name R/W Default I2C Base Address + 000h 7 BB R 0 6 RSC R 0 5 AL R 0 4 LRB R 0 3 TRX R 0 2 AAS R 0 1 GCA R 0 0 FBT R 0 All bits on this register are cleared while bit EN on CCR register is "0". Bit7 BB (Bus Busy) Indicate state of I2C-bus 0: STOP condition was detected. 1: START condition (The bus is in use.) was detected. RSC (Repeated START Condition) Indicate repeated START condition This bit is cleared by writing "0" to INT bit, the case of not addressed in a slave mode, the detection of START condition under bus stop, and the detection of STOP condition. 0: Repeated START condition was not detected. 1: START condition was detected again while the bus was in use. AL(Arbitration Lost) Detect Arbitration lost This bit is cleared by writing "0" to INT bit. 0: Arbitration lost was not detected. 1: Arbitration occurred during master transmission, or "1" writing was performed to MSS bit while other systems were using the bus. LRB (Last Received Bit) Store Acknowledge This bit is cleared by detection of START condition or STOP condition. TRX (Transmit / Receive) Indicate data receipt and data transmission. 0: receipt 1: transmission AAS (Address As Slave) Detect addressing This bit is cleared by detection of START condition or STOP condition. 0: Addressing was not performed in a slave mode. 1: Addressing was performed in a slave mode. GCA (General Call Address) Detect general call address (00h) This bit is cleared by detection of START condition or STOP condition. 0: General call address was not received in a slave mode. 1: General call address wad received in a slave mode. FBT (First Byte Transfer) Detect the 1st byte Even if this bit is set to "1" by detection of START condition, it is cleared by writing "0" on INT bit or by not being addressed in a slave mode. Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MB86296S 190 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 0: Received data is not the 1st byte. 1: Received data is the 1st byte (address data). BCR (Bus Control Register) Register address Bit No Bit field name R/W Default Bit7 I2C Base Address + 0004h 7 BER R/W0 0 6 BEIE R/W 0 5 SCC R0/W1 0 4 MSS R/W 0 3 ACK R/W 0 2 GCAA R/W 0 1 INTE R/W 0 0 INT R/W 0 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BER (Bus Error) Flag bit for request of bus error interruption When this bit is set, EN bit on CCR register will be cleared, this module will be in a stop state and data transfer will be discontinued. write case 0: A request of buss error interruption is cleared. 1: Don't care. read case 0: A bus error was not detected. 1: Undefined START condition or STOP condition was detected while data transfer. BEIE (Bus Error Interruption Enable) Permit bus error interruption When both this bit and BER bit are "1", the interruption is generated. 0: Prohibition of bus error interruption 1: Permission of bus error interruption SCC (Start Condition Continue) Generate START condition write case 0: Don't care. 1: START condition is generated again at the time of master transmission. MSS (Master Slave Select) Select master / slave mode When arbitration lost is generated in master transmission, this bit is cleared and this module becomes a slave mode. 0: This module becomes a slave mode after generating STOP condition and completing transfer. 1: This module becomes a master mode, generates START condition and starts transfer. ACK (ACKnowledge) Permit generation of acknowledge at the time of data reception This bit becomes invalid at the time of address data reception in a slave mode. 0: Acknowledge is not generated. 1: Acknowledge is generated. GCAA(General Call Address Acknowledge) Permit generation of acknowledge at the time of general call address reception 0: Acknowledge is not generated. 1: Acknowledge is generated. INTE (INTerrupt Enable) Permit interruption When this bit is "1" interruption is generated if INT bit is "1". 0: Prohibition of interrupt MB86296S 191 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 1: Permission of interrupt Bit0 INT (INTrrupt) Flag bit for request of interruption for transfer end When this bit is "1" SCL line is maintained at "L" level. If this bit is cleared by being written "0", SCL line is released and the following byte transfer is started. Moreover, it is reset to "0" by generating of START condition or STOP condition at the time of a master. write case 0: The flag is cleared. 1: Don't care. read case 0: The transfer is not ended. 1: It is set when 1 byte transfer including the acknowledge bit is completed and it corresponds to the following conditions. - It is a bus master. - It is an addressed slave. - It was going to generate START condition while other systems by which arbitration lost happened used the bus. Competition of SCC, MSS and INT bit Competition of the following byte transfer, generation of START condition and generation of STOP condition happens by the simultaneous writing of SCC, MSS and INT bit. The priority at this case is as follows. 1) The following byte transfer and generation of STOP condition If "0" is written to INT bit and "0" is written to MSS bit, priority will be given to "0" writing to MSS bit and STOP condition will be generated. 2) The following byte transfer and generation of START condition If "0" is written to INT bit and "1" is written to SCC bit, priority will be given to "1" writing to SCC bit and START condition will be generated. 3) Generation of START condition and STOP condition The simultaneous writing of "1" to SCC bit and "0" to MSS bit is prohibition. MB86296S 192 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL CCR (Clock Control Register) Register address Bit No Bit field name R/W Default Bit7 Bit6 I2C Base Address + 0008h 7 R1 1 6 HSM R/W 0 5 EN R/W 0 4 CS4 R/W 3 CS3 R/W 2 CS2 R/W 1 CS1 R/W 0 CS0 R/W - Bit5 Bit4 Nonuse "1" is always read at read. HSM (High Speed Mode) Select standard-mode / high-speed-mode 0: Standard-mode 1: High-speed-mode EN (Enable) Permission of operation When this bit is "0", each bit of BSR and BCR register (except BER and BEIE bit) is cleared. This bit is cleared when BER bit is set. 0: Prohibition of operation 1: Permission of operation CS4 - 0 (Clock Period Select4 - 0) Set up the frequency of a serial transfer clock Frequency fscl of a serial transfer clock is shown as the following formula. Please set up fscl not to exceed the value shown below at the time of master operation. standard-mode: 100KHz high-speed-mode: 400KHz standard-mode fscl = A (2 x m)+2 A int(1.5 x m)+2 high-speed-mode fscl = A: I2C system clock = 16.6MHz MB86296S 193 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL CS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 standard 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 m high-speed inhibited inhibited inhibited inhibited inhibited inhibited inhibited inhibited 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MB86296S 194 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Address Register(ADR) Register address Bit No Bit field name R/W Default Bit7 Bit6 - 0 I2C Base Address + 000Ch 7 R1 1 6 A6 R/W 5 A5 R/W 4 A4 R/W 3 A3 R/W 2 A2 R/W 1 A1 R/W 0 A0 R/W - Nonuse "1" is always read at read. A6 - 0 (Address6 - 0) Store slave address In a slave mode it is compared with DAR register after address data reception, and when in agreement, acknowledge is transmitted to a master. I2C Base Address + 0010h 7 D7 R/W 6 D6 R/W 5 D5 R/W 4 D4 R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W - Data Register(DAR) Register address Bit No Bit field name R/W Default Bit7 - 0 D7 - 0 (Data7 - 0) Store serial data This is a data register for serial data transfer. The data is transferred from MSB. At the time of data reception (TRX=0) the data output is set to "1". The writing side of this register is a double buffer. When the bus is in use (BB=1), the write data is loaded to the register for serial transfer for every transfer. At the time of read-out, the receiving data is effective only when INT bit is set because the register for serial transfer is read directly at this time. MB86296S 195 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.2.3 Graphics memory interface registers MMR (Memory I/F Mode Register) Register HostBaseAddress + FFFC H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name LOWD TRRD TRCD *1 Reserved *1 *1 TRC RW TRP TRAS RW 00 RW 000 RTS RW 000 RAW RW 000 ASW RW 0 TWR CL R/W Initial value R R1W0 R RW RW RW 00 00 RW 000 RW RW 0 0 Don't care 1 0 00 0000 *1: Reserved This register sets the mode of the graphics memory interface. A value must be written to this register after a reset. (When default setting is performed, a value must also be written to this register.) Only write once to this register; do not change the written value during operation. This register is not initialized at a software reset. Bit 2 to 0 CL (CAS Latency) Sets the CAS latency. Write the same value as this field, to the mode register for SDRAM 011 CL3 010 CL2 Other than Setting disabled the above ASW (Attached SDRAM bit Width) Sets the bit width of the data bus (memory bus width mode) 1 64 bit 0 32 bit SAW (SDRAM Address Width) Sets the bit width of the SDRAM address 001 15 bit BANK 2 bit ROW 13 bit COL 9 bit SDRAM 111 14 bit BANK 2 bit ROW 12 bit COL 9 bit SDRAM 110 14 bit BANK 2 bit ROW 12 bit COL 8 bit SDRAM 101 13 bit BANK 2 bit ROW 11 bit COL 8 bit SDRAM 100 12 bit BANK 1 bit ROW 11 bit COL 8 bit FCRAM Other than Setting disabled the above RTS (Refresh Timing Setting) Sets the refresh interval 000 Refresh is performed every 384 internal clocks. 111 Refresh is performed every 1552 internal clocks. 001 to 110 Refresh is performed every `64 x n' internal clocks in the 64 to 384 range. Bit 3 Bit 6 to 4 Bit 9 to 7 MB86296S 196 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL Bit 11 and 10 LOWD Sets the count of clocks secured for the period from the instant the ending data is output to the instant the write command is issued. 10 2 clocks Other than Setting disabled the above TRCD Sets the wait time secured from the bank active to CAS. The clock count is used to express the wait time. 11 3 clocks 10 2 clocks 01 1 clock 00 0 clock TRAS Sets the minimum time for 1 bank active. The clock count is used to express the minimum time. 111 7 clocks 110 6 clocks 101 5 clocks 100 4 clocks 011 3 clocks 010 2 clocks Other than Setting disabled the above TRP Sets the wait time secured from the pre-charge to the bank active. The clock count is used to express the wait time. 11 3 clocks 10 2 clocks 01 1 clock TRC This field sets the wait time secured from the refresh to the bank active. The clock count is used to express the wait time. 1010 10 clocks 1001 9 clocks 1000 8 clocks 0111 7 clocks 0110 6 clocks 0101 5 clocks 0100 4 clocks Bit 13 and 12 Bit 16 to 14 Bit 18 and 17 Bit 22 to 19 MB86296S 197 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 0011 3 clocks Other than Setting disabled the above Bit 24 and 23 TRRD Sets the wait time secured from the bank active to the next bank active. The clock count is used to express the wait time. 11 3 clocks 10 2 clocks Reserved Bit 26 Always write "0" at write. "1" is always read at read. Bit 30 TWR Sets the write recovery time (the time from the write command to the read or to the precharge command). 1 2 clocks 0 1 clock MB86296S 198 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL 13.2.4 Display control register DCM (Display Control Mode) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 00H (DisplayBaseAddress + 100H) 15 14 13 CKS Reserved RW RW0 0 0 12 10 9 SC RW 001110(DCM) 111101(DCME) 11 8 7 6 5 4 3 2 EEQ ODE Reserved Reserved SF ESY RW RW RX RX RW RW 0 0 X X 0 1 1 0 SYNC RW 00 This register controls the display count mode. It is not initialized by a software reset. This register is mapped to two addresses. The difference between the two registers is the format of the frequency division rate setting (SC). Bit 1 to 0 SYNC (Synchronize) Set synchronization mode X0 Non-interlace mode 10 Interlace mode 11 Interlace video mode ESY (External Synchronize) Sets external synchronization mode 0: External synchronization disabled 1: External synchronization enabled SF (Synchronize signal format) Sets format of synchronization (VSYNC, HSYNC) signals 0: Negative logic 1: Positive logic EEQ (Enable Equalizing pulse) Sets CCYNC signal mode 0: Does not insert equalizing pulse into CCYNC signal 1: Inserts equalizing pulse into CCYNC signal SC (Scaling) Divides display reference clock by the preset ratio to generate dot clock Offset = 0 Offset = 100H x00000 Frequency not divided 000000 Frequency not divided x00001 Frequency division rate = 1/4 000001 Frequency division rate = 1/2 x00010 Frequency division rate = 1/6 000010 Frequency division rate = 1/3 X00011 Frequency division rate = 1/8 000011 Frequency division rate= 1/4 : : x11111 Frequency division rate = 1/64 111111 Frequency division rate = 1/64 Bit 2 Bit 3 Bit 7 Bit 13 to 8 MB86296S 199 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL When n is set, with Offset = 0, the frequency division rate is 1/(2n + 2). When m is set, with Offset = 100h, the frequency division rate is 1/(m + 1). Basically, these are setting parameters with the same function (2n + 2 = m + 1). Because of this, m = 2n + 1 is established. When n is set to the SC field with Offset = 0, 2n + 1 is reflected with Offset = 100h. Also, when PLL is selected as the reference clock, frequency division rates 1/1 to 1/5 are non-functional even when set; other frequency division rates are assigned. Bit 15 CKS (Clock Source) Selects reference clock 0: Internal PLL output clock 1: DCLKI input MB86296S 200 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DCE (Display Controller Enable) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 02H 15 14 DEN RW 0 13 12 11 10 9 8 Reserved R0 0 7 6 5 4 3 2 1 0 L45E L23E L1E L0E RW RW RW RW 0 0 0 0 This register controls enabling the video signal output and display of each layer. Layer enabling is specified in four-layer units to maintain backward compatibility with previous products. Bit 0 L0E (L0 layer Enable) Enables display of the L0 layer. The L0 layer corresponds to the C layer for previous products. 0: Does not display L0 layer 1: Displays L0 layer L1E (L1 layer Enable) Enables display of the L1 layer. The L1 layer corresponds to the W layer for previous products. 0: Does not display L1 layer 1: Displays L1 layer L23E (L2 & L3 layer Enable) Enables simultaneous display of the L2 and L3 layers. These layers correspond to the M layer for previous products. 0: Does not display L2 and L3 layer 1: Displays L2 and L3 layer L45E (L4 & L5 layer Enable) Enables simultaneous display of the L4 and L5 layers. These layers correspond to the B layer for previous products. 0: Does not display L4 and L5 layer 1: Displays L4 and L5 layer DEN (Display Enable) Enables display 0: Does not output display signal 1: Outputs display signal Bit 1 Bit 2 Bit 3 Bit 15 MB86296S 201 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DCEE (Display Controller Extend Enable) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 102H 15 14 DEN RW 0 13 12 11 10 9 Reserved R0 0 8 7 6 5 4 3 2 1 0 L5E L4E L3E L2E L1E L0E RW RW RW RW RW RW 0 0 0 0 0 0 This register controls enabling the video signal output and display of each layer. This register has the same function as DCE. Bit 0 L0E (L0 layer Enable) Enables L0 layer display 0: Does not display L0 layer 1: Displays L0 layer L1E (L1 layer Enable) Enables L1 layer display 0: Does not display L1 layer 1: Displays L1 layer L2E (L2 layer Enable) Enables L2 layer display 0: Does not display L2 layer 1: Displays L2 layer L3E (L3 layer Enable) Enables L3 layer display 0: Does not display L3 layer 1: Displays L3 layer L4E (L4 layer Enable) Enables L4 layer display 0: Does not display L4 layer 1: Displays L4 layer L5E (L5 layer Enable) Enables L5 layer display 0: Does not display L5 layer 1: Displays L5 layer DEN (Display Enable) Enables display 0: Does not output display signal 1: Outputs display signal Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 15 MB86296S 202 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL HTP (Horizontal Total Pixels) Register DisplayBaseAddress + 06 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 HTP RW Don't care 6 4 3 2 1 0 This register controls the horizontal total pixel count. Setting value + 1 is the total pixel count. HDP (Horizontal Display Period) This register controls the total horizontal display period in unit of pixel clocks. Setting value + 1 is the pixel count for the display period. Register DisplayBaseAddress + 08 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 HDP RW Don't care 6 4 3 2 1 0 HDB (Horizontal Display Boundary) This register controls the display period of the left part of the window in unit of pixel clocks. Setting value + 1 is the pixel count for the display period of the left part of the window. When the window is not divided into right and left before display, set the same value as HDP. Register DisplayBaseAddress + 0A H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 HDB RW Don't care 6 4 3 2 1 0 HSP (Horizontal Synchronize pulse Position) Register DisplayBaseAddress + 0C H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 HSP RW Don't care 6 4 3 2 1 0 This register controls the pulse position of the horizontal synchronization signal in unit of pixel clocks. When the clock count since the start of the display period reaches setting value + 1, the horizontal synchronization signal is asserted. HSW (Horizontal Synchronize pulse Width) Register DisplayBaseAddress + 0E H address Bit number 7 6 5 Bit field name R/W Initial value 4 HSW RW Don't care 3 2 1 0 This register controls the pulse width of the horizontal synchronization signal in unit of pixel clocks. Setting value + 1 is the pulse width clock count. MB86296S 203 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL VSW (Vertical Synchronize pulse Width) Register DisplayBaseAddress + 0F H address Bit number 7 6 5 Bit field name Reserved R/W R0 Initial value 0 4 3 VSW RW Don't care 2 1 0 This register controls the pulse width of vertical synchronization signal in unit of raster. Setting value + 1 is the pulse width raster count. VTR (Vertical Total Rasters) Register DisplayBaseAddress + 12 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 VTR RW Don't care 6 4 3 2 1 0 This register controls the vertical total raster count. Setting value + 1 is the total raster count. For the interlace display, Setting value + 1.5 is the total raster count for 1 field; 2 x setting value + 3 is the total raster count for 1 frame (see Section 8.3.2). VSP (Vertical Synchronize pulse Position) This register controls the pulse position of vertical synchronization signal in unit of raster. The vertical synchronization pulse is asserted starting at the setting value + 1st raster relative to the display start raster. Register DisplayBaseAddress + 14 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 VSP RW Don't care 6 4 3 2 1 0 VDP (Vertical Display Period) This register controls the vertical display period in unit of raster. Setting value + 1 is the count of raster to be displayed. Register DisplayBaseAddress + 16 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 5 VDP RW Don't care 6 4 3 2 1 0 MB86296S 204 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L0M (L0 layer Mode) Register DisplayBaseAddress + 20 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0C Reserved R0 0 CW RW Don't care Reserved R0 0 CH RW Don't care Initial value 0 Bit 11 to 0 RW R/W R0 0 L0H (L0 layer Height) Specifies the height of the logic frame of the L0 layer in pixel units. Setting value + 1 is the height L0W (L0 layer memory Width ) Sets the memory width (stride) of the logic frame of the L0 layer in 64-byte units L0C (L0 layer Color mode) Sets the color mode for L0 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode Bit 23 to 16 Bit 31 L0EM (L0-layer Extended Mode) L0EC RW Reserved R0 0 L0PB RW Reserved R0 0 R/W Initial value Bit 0 L0 WP (L0 layer Window Position enable) Selects the display position of L0 layer 0 Compatibility mode display (C layer supported) 1 Window display L0PB (L0 layer Palette Base) Shows the value added to the index when subtracting palette of L0 layer. 16 times of setting value is added. L0EC (L0 layer Extended Color mode) Sets extended color mode for L0 layer 00 Mode determined by L0C 01 Direct color (24 bits/pixel) mode 1x Reserved Bit 23 to 20 Bit 31 and 30 MB86296S 205 L0WP RW 0 Register DisplayBaseAddress + 110 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----Bit field name 432 1 0 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL MB86296S 206 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L0OA (L0 layer Origin Address) Register DisplayBaseAddress + 24 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0OA R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L0 layer. Since lower 4 bits are fixed at "0", address 16-byte-aligned. L0DA (L0-layer Display Address) This register sets the display origin address of the L0 layer. For the direct color mode (16 bits/pixel), the lower 1 bit is "0", and this address is treated as being aligned in 2 bytes. Register DisplayBaseAddress + 28 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0DA R/W R0 RW Initial value 0 Don't care L0DX (L0-layer Display position X) This register sets the display starting position (X coordinates) of the L0 layer on the basis of the origin of the logic frame in pixels. Register DisplayBaseAddress + 2C H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0DX RW Don't care 4 3 2 1 0 L0DY (L0-layer Display position Y) This register sets the display starting position (Y coordinates) of the L0 layer on the basis of the origin of the logic frame in pixels. Register DisplayBaseAddress + 2E H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0DY RW Don't care 4 3 2 1 0 MB86296S 207 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L0WX (L0 layer Window position X) Register DisplayBaseAddress + 114 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WX RW 4 3 2 1 0 This register sets the X coordinates of the display position of the L0 layer window. L0WY (L0 layer Window position Y) This register sets the Y coordinates of the display position of the L0 layer window. Register DisplayBaseAddress + 116 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WY RW 4 3 2 1 0 L0WW (L0 layer Window Width) This register controls the horizontal direction display size (width) of the L0 layer window. Do not specify "0". Register DisplayBaseAddress + 118 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WW RW Don't care 4 3 2 1 0 L0WH (L0 layer Window Height) This register controls the vertical direction display size (height) of the L0 layer window. Setting value + 1 is the height. Register DisplayBaseAddress + 11A H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WH RW Don't care 4 3 2 1 0 MB86296S 208 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L1M (L1-layer Mode) Register DisplayBaseAddress + 30 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name L1C L1YC L1CS L1IM Reserved L1W --- 543210 Reserved R0 0 R/W Initial value Bit 23 to 16 L1W (L1 layer memory Width) Sets the memory width (stride) of the logic frame of the W layer in unit of 64 bytes L1IM (L1 layer Interlace Mode) Sets video capture mode when L1CS in capture mode 0: Normal mode 1: For non-interlace display, displays captured video graphics in WEAVE mode For interlace and video display, buffers are managed in frame units (pair of odd field and even field). L1CS ( 1 layer Capture Synchronize) L Sets whether the layer is used as normal display layer or as video capture 0: Normal mode 1: Capture mode L1YC (L1 layer YC mode) Sets color format of L1 layer The YC mode must be set for video capture. 0: RGB mode 1: YC mode L1C ( 1 layer Color mode) L Sets color mode for L1 layer 0: Indirect color (8 bits/pixel) mode 1: Direct color (16 bits/pixel) mode Bit 28 Bit 29 Bit 30 Bit 31 MB86296S 209 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L1EM (L1 layer Extended Mode) Register address Bit number Bit field name R/W Initial value DisplayBaseAddress + 120H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - L1EC Reserved DM L1PB Reserved RW R0 RW R0 0 0 432 1 0 Bit 23 to 20 Bit 25 to 24 Bit 31 to 30 L1PB (L1 layer Palette Base) Shows the value added to the index when subtracting palette of L1 layer. 16 times of setting value is added. L1DM (L1 layer Display Magnify Mode) 00 Normal Mode (no scaling or shrink scaling) 01 Reserved 10 Magnify Scaling 11 Reserved L1EC (L1 layer Extended Color mode) Sets extended color mode for L1 layer 00 Mode determined by L1C 01 Direct color (24 bits/pixel) mode 1x Reserved L1DA (L1 layer Display Address) Register DisplayBaseAddress + 34 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L1DA R/W R0 RW Initial value 0 Don't care This register sets the display origin address of the L1 layer. For the direct color mode (16 bits/pixel), the lower 1 bit is "0", and this register is treated as being aligned in 2 bytes. Wraparound processing is not performed for the L1 layer, so the frame origin linear address and display position (X coordinates, and Y coordinates) are not specified. L1WX (L1 layer Window position X) This register sets the X coordinates of the display position of the L1 layer window. This register is placed in two address spaces. The parenthesized address is the register address to maintain compatibility with previous products. The same applies to L1WY, L1WW, and L1WH. Register DisplayBaseAddress + 124 (DisplayBaseAddress + 18 ) H H address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WX R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 L1WY (L1 layer Window position Y) Register DisplayBaseAddress + 126 (DisplayBaseAddress + 1A ) H H address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WY R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 MB86296S This register sets the Y coordinates of the display position of the L1 layer window. 210 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L1WW (L1 layer Window Width) Register DisplayBaseAddress + 128 (DisplayBaseAddress + 1C ) H H address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WW R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 This register controls the horizontal direction display size (width) of the L1 layer window. Do not specify "0". L1WH (L1 layer Window Height) This register controls the vertical direction display size (height) of the L1 layer window. Setting value + 1 is the height. Register DisplayBaseAddress + 12A ((DisplayBaseAddress + 1E ) H H address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WH R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 L1CR0 (L1 layer Coefficient for Red 0) This register defines YCbCr/RGB converstion parameters for red component. Bit 10 to 0 a11 11bit signed real. lower8bit is fraction. two's complement. a12 11bit signed real. lower8bit is fraction. two's complement. Register DisplayBaseAddress + 1E0 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved a12 Reserved a11 R/W R0 RW R0 RW Initial value 0 000 0000 0000 0 001 0010 1011 Bit 26 to 16 Refer 7.7 for detail. MB86296S 211 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L1CR1 (L1 layer Coefficient for Red 1) Register DisplayBaseAddress + 1E4 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b1 Reserved a13 R/W R0 RW R0 RW Initial value 0 1 1111 0000 0 001 1001 1000 This register defines YCbCr/RGB converstion parameters for red component. Bit 10 to 0 a13 11bit signed real. lower8bit is fraction. two's complement. b1 9bit signed integer. two's complement. Bit 24 to 16 Refer 7.7 for detail. L1CG0 (L1 layer Coefficient for Green 0) This register defines YCbCr/RGB converstion parameters for green component. Bit 10 to 0 a21 11bit signed real. lower8bit is fraction. two's complement. a22 11bit signed real. lower8bit is fraction. two's complement. Register DisplayBaseAddress + 1E8 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved a22 Reserved a21 R/W R0 RW R0 RW Initial value 0 111 1001 1100 0 001 0010 1011 Bit 26 to 16 Refer 7.7 for detail. MB86296S 212 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L1CG1 (L1 layer Coefficient for Green 1) Register DisplayBaseAddress + 1EC H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b2 Reserved a23 R/W R0 RW R0 RW Initial value 0 1 1111 0000 0 111 0010 1111 This register defines YCbCr/RGB converstion parameters for green component. Bit 10 to 0 Bit 24 to 16 a23 11bit signed real. lower8bit is fraction. two's complement. b2 9bit signed integer. two's complement. Refer 7.7 for detail. L1CB0 (L1 layer Coefficient for Blue 0) This register defines YCbCr/RGB converstion parameters for blue component. Bit 10 to 0 Bit 26 to 16 a31 11bit signed real. lower8bit is fraction. two's complement. a32 11bit signed real. lower8bit is fraction. two's complement. Register DisplayBaseAddress + 1F0 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved a32 Reserved a31 R/W R0 RW R0 RW Initial value 0 010 0000 0100 0 001 0010 1011 Refer 7.7 for detail. L1CB1 (L1 layer Coefficient for Blue 1) This register defines YCbCr/RGB converstion parameters for blue component. Bit 10 to 0 a33 11bit signed real. lower8bit is fraction. two's complement. b3 9bit signed integer. two's complement. Register DisplayBaseAddress + 1F4 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b3 Reserved a33 R/W R0 RW R0 RW Initial value 0 1 1111 0000 0 000 0000 0000 Bit 24 to 16 Refer 7.7 for detail. MB86296S 213 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L2M (L2 layer Mode) Register DisplayBaseAddress + 40 H address Bit number 31 30 29 28 27 - - 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L2FLP L2C Reserved R0 0 L2W RW Don't care Reserved R0 0 L2H RW Don't care Initial value Bit 11 to 0 Bit 23 to 16 Bit 30 and 29 L2FLP (L2 layer Flip mode) Sets flipping mode for L2 layer 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved Bit 31 L2C (L2 layer Color mode) Sets the color mode for L2 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode MB86296S RW R/W RW L2H (L2 layer Height) Specifies the height of the logic frame of the L2 layer in pixel units. Setting value + 1 is the height L2W (L2 layer memory Width) Sets the memory width (stride) of the logic frame of the L2 layer in 64-byte units 214 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L2EM (L2 layer Extended Mode) Register DisplayBaseAddress + 130 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----Reserved R0 0 L2PB RW 0 Reserved R0 0 432 1 L2OM 0 L0WP Bit field name L2EC R/W Initial value Bit 0 RW 00 RW RW 00 L2 WP (L2 layer Window Position enable) Selects the display position of L2 layer 0 Compatibility mode display (ML layer supported) 1 Window display L2OM (L2 layer Overlay Mode) Selects the overlay mode for L2 layer 0 Compatibility mode 1 Extended mode L2PB (L2 layer Palette Base) Shows the value added to the index when subtracting palette of L2 layer. 16 times of setting value is added. L2EC (L2 layer Extended Color mode) Sets extended color mode for L2 layer 00 Mode determined by L2C 01 Direct color (24 bits/pixel) mode 1x Reserved Bit 1 Bit 23 to 20 Bit 31 and 30 MB86296S 215 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L2OA0 (L2 layer Origin Address 0) Register DisplayBaseAddress + 44 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L2 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L2DA0 (L2 layer Display Address 0) Register DisplayBaseAddress + 48 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L2 layer in frame 0. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L2OA1 (L2 layer Origin Address 1) Register DisplayBaseAddress + 4C H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L2 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L2DA1 (L2 layer Display Address 1) Register DisplayBaseAddress + 50 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L2 layer in frame 1. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L2DX (L2 layer Display position X) Register DisplayBaseAddress + 54 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L2 layer on the basis of the origin of the logic frame in pixels. MB86296S 216 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L2DY (L2 layer Display position Y) Register DisplayBaseAddress + 56 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L2 layer on the basis of the origin of the logic frame in pixels. L2WX (L2 layer Window position X) This register sets the X coordinates of the display position of the L2 layer window. Register DisplayBaseAddress + 134 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WX RW Don't care 4 3 2 1 0 L2WY (L2 layer Window position Y) This register sets the Y coordinates of the display position of the L2 layer window. Register DisplayBaseAddress + 138 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WY RW Don't care 4 3 2 1 0 L2WW (L2 layer Window Width) Register DisplayBaseAddress + 13A H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size (width) of the L2 layer window. Do not specify "0". L2WH (L2 layer Window Height) Register DisplayBaseAddress + 13C H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L2 layer window. Setting value + 1 is the height. MB86296S 217 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L3M (L3 layer Mode) Register DisplayBaseAddress + 58 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L3C L3FLP Reserved L3W Reserved L3H R/W RW R0 R0 RW R0 RW Initial value 0 0 0 Don't care 0 Don't care Bit 11 to 0 L3H ( 3 layer Height) L Specifies the height of the logic frame of the L3 layer in pixel units. Setting value + 1 is the height L3W (L3 layer memory Width) Sets the memory width (stride) of the logic frame of the L3 layer in 64-byte units L3FLP (L3 layer Flip mode) Sets flipping mode for L3 layer 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved L3C ( 3 layer Color mode) L Sets the color mode for L3 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode Bit 23 to 16 Bit 30 and 29 Bit 31 MB86296S 218 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L3EM (L3 layer Extended Mode) Register address Bit number Bit field name R/W Initial value Bit 0 DisplayBaseAddress + 140H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 L3EC Reserved L3PB Reserved RW R0 RW R0 00 0 0 0 --- 432 1 L3OM L3WP 0 RW RW 0 L3 WP (L3 layer Window Position enable) Selects the display position of L3 layer 0 Compatibility mode display (MR layer supported) 1 Window display L3OM (L3 layer Overlay Mode) Selects the overlay mode for L3 layer 0 Compatibility mode 1 Extended mode L3PB (L3 layer Palette Base) Shows the value added to the index when subtracting palette of L3 layer. 16 times of setting value is added. L3EC (L3 layer Extended Color mode) Sets extended color mode for L3 layer 00 Mode determined by L3C 01 Direct color (24 bits/pixel) mode 1x Reserved Bit 1 Bit 23 to 20 Bit 31 and 30 MB86296S 219 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L3OA0 (L3 layer Origin Address 0) Register DisplayBaseAddress + 5C H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L3 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L3DA0 (L3 layer Display Address 0) Register DisplayBaseAddress + 60 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L3 layer in frame 0. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L3OA1 (L3 layer Origin Address 1) Register DisplayBaseAddress + 64 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L3 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L3OA1 (L3 layer Display Address 1) Register DisplayBaseAddress + 68 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L3 layer in frame 1. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L3DX (L3 layer Display position X) Register DisplayBaseAddress + 6C H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L3 layer on the basis of the origin of the logic frame in pixels. MB86296S 220 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L3DY (L3 layer Display position Y) Register DisplayBaseAddress + 6E H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L3 layer on the basis of the origin of the logic frame in pixels. L3WX (L3 layer Window position X) This register sets the X coordinates of the display position of the L3 layer window. Register DisplayBaseAddress + 140 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WX RW Don't care 4 3 2 1 0 L3WY (L3 layer Window position Y) This register sets the Y coordinates of the display position of the L3 layer window. Register DisplayBaseAddress + 142 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WY RW Don't care 4 3 2 1 0 L3WW (L3 layer Window Width) Register DisplayBaseAddress + 144 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size (width) of the L3 layer window. Do not specify "0". L3WH (L3-layer Window Height) Register DisplayBaseAddress + 146 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L3 layer window. Setting value + 1 is the height. MB86296S 221 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L4M (L4 layer Mode) Register DisplayBaseAddress + 70 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L4C L4FLP Reserved L4W Reserved L4H R/W RW RW R0 RW R0 RW Initial value 0 Don't care 0 Don't care Bit 11 to 0 L4H (L4 layer Height) Specifies the height of the logic frame of the L4 layer in pixel units. Setting value + 1 is the height L4W (L4 layer memory Width ) Sets the memory width (stride) logic frame of the L4 layer in 64-byte units L4FLP (L4 layer Flip mode) Sets flipping mode for L4 layer 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved L4C (L4 layer Color mode) Sets the color mode for L4 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode Bit 23 to 16 Bit 30 and 29 Bit 31 MB86296S 222 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L4EM (L4 layer Extended Mode) Register address Bit number Bit field name R/W Initial value Bit 0 DisplayBaseAddress + 150H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 L4EC Reserved L4PB Reserved RW R0 RW R0 00 0 0 0 --- 432 1 L4OM L4WP 0 RW RW 0 L4 WP (L4 layer Window Position enable) Selects the display position of L4 layer 0 Compatibility mode display (BL layer supported) 1 Window display L4OM (L4 layer Overlay Mode) Selects the overlay mode for L4 layer 0 Compatibility mode 1 Extended mode L4PB (L4 layer Palette Base) Shows the value added to the index when subtracting palette of L4 layer. 16 times of setting value is added. L4EC (L4 layer Extended Color mode) Sets extended color mode for L4 layer 00 Mode determined by L4C 01 Direct color (24 bits/pixel) mode 1x Reserved Bit 1 Bit 23 to 20 Bit 31 and 30 MB86296S 223 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L4OA0 (L4 layer Origin Address 0) Register DisplayBaseAddress + 74 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L4 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L4DA0 (L4 layer Display Address 0) Register DisplayBaseAddress + 78 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L4 layer in frame 0. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L4OA1 (L4 layer Origin Address 1) Register DisplayBaseAddress + 7C H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L4 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L4OA1 (L4 layer Display Address 1) Register DisplayBaseAddress + 80 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L4 layer in frame 1. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L4DX (L4 layer Display position X) Register DisplayBaseAddress + 84 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L4 layer on the basis of the origin of the logic frame in pixels. MB86296S 224 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L4DY (L4 layer Display position Y) Register DisplayBaseAddress + 86 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L4 layer on the basis of the origin of the logic frame in pixels. L4WX (L4 layer Window position X) This register sets the X coordinates of the display position of the L4 layer window. Register DisplayBaseAddress + 154 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WX RW Don't care 4 3 2 1 0 L4WY (L4 layer Window position Y) This register sets the Y coordinates of the display position of the L4 layer window. Register DisplayBaseAddress + 156 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WY RW Don't care 4 3 2 1 0 L4WW (L4 layer Window Width) Register DisplayBaseAddress + 158 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size (width) of the L4 layer window. Do not specify "0". L4WH (L4 layer Window Height) Register DisplayBaseAddress + 15A H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L4 layer window. Setting value + 1 is the height. MB86296S 225 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L5M (L5 layer Mode) Register DisplayBaseAddress + 88 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L5C L5FLP Reserved L5W Reserved L5H R/W RW RW R0 RW R0 RW Initial value 0 Don't care 0 Don't care Bit 11 to 0 L5H (L5 layer Height) Specifies the height of the logic frame of the L5 layer in pixel units. Setting value + 1 is the height L5W (L5 layer memory Width) Sets the memory width (stride) logic frame of the L5 layer in 64-byte units L5FLP (L5 layer Flip mode) Sets flipping mode for L5 layer 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved L5C (L5 layer Color mode) Sets the color mode for L5 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode Bit 23 to 16 Bit 30 and 29 Bit 31 MB86296S 226 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L5EM (L5 layer Extended Mode) Register address Bit number Bit field name R/W Initial value Bit 0 DisplayBaseAddress + 110H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 L5EC Reserved L5PB Reserved RW R0 RW R0 00 0 0 0 --- 432 1 L5OM L5WP 0 RW RW 0 L5 WP (L5 layer Window Position enable) Selects the display position of L5 layer 0 Compatibility mode display (BR layer supported) 1 Window display L5OM (L5 layer Overlay Mode) Selects the overlay mode for L5 layer 0 Compatibility mode 1 Extended mode L5PB (L5 layer Palette Base) Shows the value added to the index when subtracting palette of L5 layer. 16 times of setting value is added. L5EC (L5 layer Extended Color mode) Sets extended color mode for L5 layer 00 Mode determined by L5C 01 Direct color (24 bits/pixel) mode 1x Reserved Bit 1 Bit 23 to 20 Bit 31 to 30 MB86296S 227 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L5OA0 (L5 layer Origin Address 0) Register DisplayBaseAddress + 8C H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved BROA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L5 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L5DA0 (L5 layer Display Address 0) Register DisplayBaseAddress + 90 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L5 layer in frame 0. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L5OA1 (L5 layer Origin Address 1) Register DisplayBaseAddress + 94 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L5 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L5OA1 (L5 layer Display Address 1) Register DisplayBaseAddress + 98 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L5 layer in frame 1. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L5DX (L5 layer Display position X) Register DisplayBaseAddress + 9C H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L5 layer on the basis of the origin of the logic frame in pixels. MB86296S 228 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L5DY (L5 layer Display position Y) Register DisplayBaseAddress + 9E H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L5 layer on the basis of the origin of the logic frame in pixels. L5WX (L5 layer Window position X) This register sets the X coordinates of the display position of the L5 layer window. Register DisplayBaseAddress + 164 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WX RW Don't care 4 3 2 1 0 L5WY (L5 layer Window position Y) This register sets the Y coordinates of the display position of the L5 layer window. Register DisplayBaseAddress + 166 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WY RW Don't care 4 3 2 1 0 L5WW (L5 layer Window Width) Register DisplayBaseAddress + 168 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WW RW Don't care 4 3 2 1 0 This register controls the horizontal direction display size (width) of the L5 layer window. Do not specify "0". L5WH (L5 layer Window Height) Register DisplayBaseAddress + 16A H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L5 layer window. Setting value + 1 is the height. MB86296S 229 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL CUTC (Cursor Transparent Control) Register DisplayBaseAddress + A0 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 Bit 7 to 0 9 8 7 CUZT RW Don't care 6 5 4 3 CUTC RW Don't care 2 1 0 CUTC (Cursor Transparent Code) Sets color code handled as transparent code CUZT (Cursor Zero Transparency) Defines handling of color code 0 0 Code 0 as non-transparency color 1 Code 0 as transparency color Bit 8 CPM (Cursor Priority Mode) This register controls the display priority of cursors. Cursor 0 is always preferred to cursor 1. Bit 0 CUO0 (Cursor Overlap 0) Sets display priority between cursor 0 and pixels of Console layer 0 Puts cursor 0 atlower than L0 layer. 1 Puts cursor 0 athigher than L0 layer. CUO1 (Cursor Overlap 1) Sets display priority between cursor 1 and C layer 0 Puts cursor 1 atlo wer than L0 layer. 1 Puts cursor 1 atlower than L0 layer. CEN0 (Cursor Enable 0) Sets enabling display of cursor 0 0 Disabled 1 Enabled CEN1 (Cursor Enable 1) Sets enabling display of cursor 1 0 Disabled 1 Enabled Register DisplayBaseAddress + A2 H address Bit number 7 6 5 Bit field name Reserved CEN1 R/W R0 RW Initial value 0 0 4 CEN0 RW 0 3 Reserved R0 0 2 1 CUO1 RW 0 0 CUO0 RW 0 Bit 1 Bit 4 Bit 5 MB86296S 230 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL CUOA0 (Cursor-0 Origin Address) Register DisplayBaseAddress + A4 H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CUOA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the start address of the cursor 0 pattern. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. Register DisplayBaseAddress + A8 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 CUX0 (Cursor-0 X position) 9 8 7 6 5 CUX0 RW Don't care 4 3 2 1 0 This register sets the display position (X coordinates) of the cursor 0 in pixels. The reference position of the coordinates is the top left of the cursor pattern. CUY0 (Cursor-0 Y position) This register sets the display position (Y coordinates) of the cursor 0 in pixels. The reference position of the coordinates is the top left of the cursor pattern. Register DisplayBaseAddress + Aa H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 CUY0 RW Don't care 4 3 2 1 0 MB86296S 231 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL CUOA1 (Cursor-1 Origin Address) Register DisplayBaseAddress + AC H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CUOA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the start address of the cursor 1 pattern. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. CUX1 (Cursor-1 X position) Register DisplayBaseAddress + B0 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 CUX1 RW Don't care 4 3 2 1 0 This register sets the display position (X coordinates) of the cursor 1 in pixels. The reference position of the coordinates is the top left of the cursor pattern. CUY1 (Cursor-1 Y position) Register DisplayBaseAddress + B2 H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 CUY1 RW Don't care 4 3 2 1 0 This register sets the display position (Y coordinates) of the cursor 1 in pixels. The reference position of the coordinates is the top left of the cursor pattern. MB86296S 232 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DLS (Display Layer Select) Register DisplayBaseAddress + 180 H address Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved DLS5 DLS4 DLS3 DLS2 DLS1 DSL0 R/W R0 R0 RW R0 RW R0 RW R0 RW R0 RW R0 RW Initial value 101 100 011 010 001 000 This register defines the blending sequence. Bit 3 to 0 DSL0 (Display Layer Select 0) Selects the top layer subjected to blending. 0000 L0 layer 0001 L1 layer : : 0101 L5 layer 0110 Reserved : : 0110 Reserved 0111 Not selected DSL1 (Display Layer Select 1) Selects the second layer subjected to blending. The bit values are the same as DSL0. DSL2 (Display Layer Select 2) Selects the third layer subjected to blending. The bit values are the same as DSL0. DSL3 (Display Layer Select 3) Selects the fourth layer subjected to blending. The bit values are the same as DSL0. DSL4 (Display Layer Select 4) Selects the fifth layer subjected to blending. The bit values are the same as DSL0. DSL5 (Display Layer Select 5) Selects the bottom layer subjected to blending. The bit values are the same as DSL0. Bit 7 to 4 Bit 11 to 8 Bit 15 to 12 Bit 19 to 16 Bit 23 to 20 MB86296S 233 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL DBGC (Display Background Color) Register DisplayBaseAddress + 184 H address Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved DBGR DBGG DBGB R/W R0 Initial value This register specifies the color to be displayed in areas outside the display area of each layer on the window. Bit 7 to 0 DBGB (Display Background Blue) Specifies the blue level of the background color. DBGG (Display Background Green) Specifies the green level of the background color. DBGR (Display Background Red) Specifies the red level of the background color. Bit 15 to 8 Bit 23 to 16 MB86296S 234 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L0BLD (L0 Blend) Register DisplayBaseAddress + B4 H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0BE L0BS L0BI L0BP Reserved L0BR R/W Initial value This register specifies the blend parameters for the L0 layer. This register corresponds to BRATIO or BMODE for previous products. Bit 7 to 0 L0BR (L0 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. L0BP (L0 layer Blend Plane) Specifies that the L5 layer is the blend plane. 0 Value of L0BR used as blend ratio 1 Pixel of L5 layer used as blend ratio L0BI (L0 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L0BS (L0 layer Blend Select) Selects the blend calculation expression. 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L0BE (L0 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Bit 13 Bit 14 Bit 15 Bit 16 Before blending, the blend mode must be specified using L0BE, and alpha must also be enabled for L0 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86296S 235 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L1BLD (L1 Blend) Register DisplayBaseAddress + 188 H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L1BE L1BS L1BI L1BP Reserved L1BR R/W Initial value This register specifies the blend parameters for the L1 layer. Bit 7 to 0 L1BR (L1 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. L1BP (L1 layer Blend Plane) Specifies that the L5 layer is the blend plane. 0 Value of L1BR used as blend ratio 1 Pixel of L5 layer used as blend ratio L1BI (L1 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L1BS (L1 layer Blend Select) Selects the blend calculation expression. 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L1BE (L1 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Bit 13 Bit 14 Bit 15 Bit 16 Before blending, the blend mode must be specified using L1BE, and alpha must also be enabled for L1 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86296S 236 FUJITSU LIMITED PRELIMINARY AND CONFIDENTIAL L2BLD (L2 Blend) Register DisplayBaseAddress + 18C H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2BE L2BS L2BI L2BP Reserved L2BR R/W Initial value This register specifies the blend parameters for the L2 layer. Bit 7 to 0 L2BR (L2 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. L2BP (L2 layer Blend Plane) Specifies that the L5 layer is the blend plane. 0 Value of L2BR used as blend ratio 1 Pixel of L5 layer used as blend ratio L2BI (L2 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L2BS (L2 layer Blend Select) Selects the blend calculation expression. 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L2BE (L2 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Bit 13 Bit 14 Bit 15 Bit 16 Before blending, the blend mode must be specified using L2BE, and alpha must also be enabled for L2 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86296S |